Periphery clock distribution network for a programmable...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S295000, C326S037000, C326S039000, C326S041000, C326S047000

Reexamination Certificate

active

07737751

ABSTRACT:
A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.

REFERENCES:
patent: 5394033 (1995-02-01), Tsui et al.
patent: 5712579 (1998-01-01), Duong et al.
patent: 5717229 (1998-02-01), Zhu
patent: 5815726 (1998-09-01), Cliff
patent: 5892370 (1999-04-01), Eaton et al.
patent: 5903165 (1999-05-01), Jones et al.
patent: 6006025 (1999-12-01), Cook et al.
patent: 6191609 (2001-02-01), Chan et al.
patent: 6292930 (2001-09-01), Agrawal et al.
patent: 6353352 (2002-03-01), Sharpe-Geisler
patent: 6426649 (2002-07-01), Fu et al.
patent: 6480025 (2002-11-01), Altaf
patent: 6573757 (2003-06-01), Gallagher
patent: 6701507 (2004-03-01), Srinivasan
patent: 6867616 (2005-03-01), Venkata et al.
patent: 6996736 (2006-02-01), Nguyen et al.
patent: 7075365 (2006-07-01), Starr et al.
patent: 7145362 (2006-12-01), Bergendahl et al.
patent: 7167023 (2007-01-01), Pan et al.
patent: 2003/0101423 (2003-05-01), Thorp et al.
patent: 2006/0006918 (2006-01-01), Saint-Laurent

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Periphery clock distribution network for a programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Periphery clock distribution network for a programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Periphery clock distribution network for a programmable... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4248053

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.