Patent
1996-11-18
1999-01-19
Ray, Gopal C.
395828, 395284, G06F 1310, G06F 1300
Patent
active
058624058
ABSTRACT:
A unit address is automatically set in a peripheral unit. A plurality of peripheral units 1 are connected to a CPU unit via a signal line 3. The CPU unit accesses each peripheral unit 1 by individually selecting the peripheral units. The signal line 3 is provided with a first signal line 31 for transmitting an address by bus connection of the peripheral units and a second signal 32 line for transmitting a write command signal by cascade connection of the peripheral units 1. The write command signal is sequentially transmitted in the order in which the peripheral units 1 are connected, and only the peripheral unit 1 that has received the write command signal receives a unit address and retains it in a latch circuit 11a.
REFERENCES:
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patent: 4573120 (1986-02-01), Ichimiya et al.
patent: 5301276 (1994-04-01), Kimura
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5551053 (1996-08-01), Nadolski et al.
Fukuda Atsuo
Masuo Yasuo
Matsushita Electric & Works Ltd.
Ray Gopal C.
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