Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With means to increase breakdown voltage
Reexamination Certificate
2001-10-09
2002-10-01
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With means to increase breakdown voltage
C257S169000, C257S171000, C257S578000, C257S566000, C257S577000, C257S583000, C257S584000
Reexamination Certificate
active
06459102
ABSTRACT:
Peripheral structure for monolithic power device This invention concerns a peripheral structure for a monolithic power device.
Conventional integrated circuits usually differentiate themselves by the layout of masks. They are thus frozen vertically and therefore little suited for power integration evolution. Consequently, in order to create new power functions, structures made of technological bricks compatible among themselves, are used preferably.
Thus, integrated components for monolithic power device in planar technology are known. It is essential that such components exhibit good voltage handling, i.e. they have a maximum electric field before avalanche breakdown that is sufficiently high to sustain the voltages desired, while remaining smaller than the critical electric field. The maximum electric field must be controllable when designing and manufacturing the component.
This control relies for the whole semi-conductor power devices known on so-called ‘guard’ solutions, based upon a spread of equipotential lines at the surface of the component and at the junction levels.
Thus, mesa-type techniques consist of mechanical chamfering of a junction to be protected. However, these techniques are hardly compatible with planar processes enabling the realisation of integrated complex power devices. Moreover, it excludes MOS technology processes, such as IGBT (Insulated Gate Bipolar Transistor) bipolar-MOS or MCT (MOS Controlled Thyristor) thyristor-MOS technologies.
Other guard techniques implement guard rings, field electrodes or field plates, semi-resistive layers or P-junction terminations (JTE—Junction Termination Extension). The junction termination type technique, notably, consists of an implantation of a little doped P-region, all around a main junction to be protected and in contact with the said junction. The integrated components using these different guard techniques comprise generally insulating boxes formed laterally in the component and with a shrunk central portion, as well as a stop channel for the potential lines between the main junction and one of the diffusions of the insulating box.
A shortcoming of these guard techniques is that they require a minimum surface in order to control the maximum electric field. Moreover, the manufacture is made more complicated by the necessity of implanting a stop channel. The components using these guard techniques exhibit moreover dissymmetrical voltage handling and therefore constitute technological bricks with reduced reach.
In particular, certain devices exhibit a rear-faced junction, connected physically to lateral insulating boxes, and a front-faced junction, protected by one of the guard techniques and surrounded laterally by stop channels. When the front junction is reverse-biased, the equipotential lines are blocked at the stop channels and do not reach the insulating boxes, whereas when the rear junction is reverse-biased, the equipotential lines rise towards the front face through the insulating boxes.
Besides the shortcomings mentioned, this realisation only enables to introduce elementary electric functions in the box delineated by the rear junction.
This invention concerns a peripheral structure for a monolithic power device with smaller space requirements than the components known for equal value of the critical electric field and enabling the implantation of electric functions at the front face and at the rear face.
The structure of the invention is compatible with a planar technology and enables good control of the electric field.
The invention also concerns such a peripheral structure that does not require any stop channels and that can be used with a MOS technology.
The peripheral structure according to the invention can also enable to sustain symmetrical voltages and thus be particularly supple to be used as a technological brick. This brick enables voltage symmetrisation of existing power components, such as power bipolar transistors, thyristors or IGBT components, but also the design and realisation of new components or of new power electric functions.
To that effect, the invention concerns a peripheral structure for monolithic power device comprising:
a substrate with a first doping type,
a front face fitted with a connection with a cathode,
a rear face fitted with a connection with an anode,
a first junction adjoining one of the faces, whereas this junction is reverse-biased when a direct voltage is applied between the anode and the cathode,
a second junction adjoining the face opposite to the face corresponding to the first junction, whereas this junction is forward-biased when a direct voltage is applied between the anode and the cathode,
at least one insulating box with a second type of doping, connecting the front and rear face and disconnected electrically from the first junction.
The structure is such that when a reverse voltage is applied between the anode and the cathode, creating equipotential voltage lines, the insulating box enables to distribute the equipotential lines in the substrate.
According to the invention, the insulating box is disconnected electrically from the second junction and the peripheral structure is such that when a direct voltage is applied between the anode and the cathode, generating equipotential voltage lines, the insulating box enables to distribute the said equipotential lines in the substrate.
Thus, conversely to known guard techniques, the insulating box(es) fulfil in the invention a distribution function of the equipotential lines in the substrate, i.e. in the volume of the structure, in both biasing directions. Thanks to that distribution, a stop channel proves superfluous and the sizes of the component can be reduced with respect to the existing ones. Besides, electric functions can be implanted on both front and rear faces. Indeed, the anode and the cathode are not in electrical contact with the insulating boxes.
The structure is also capable of sustaining symmetrical voltages. These voltages range for instance between 600 and 1200 V. In some embodiments, they reach values between 4000 and 5000 V.
Preferably, the peripheral structure comprises two lateral insulating boxes, arranged symmetrically with respect to the junctions. However, according to an embodiment variation, it comprises a single lateral insulating box on one side of the junctions, whereas another technique is used on the second side.
The peripheral structure of the invention is used advantageously in a functional integration mode, for which the power function grows out of electrical interactions between arranged and sized semi-conductor regions and also out of surface interconnections. This integration mode is particularly suited to high voltage applications, notably for connections to an electrical energy distribution network calling for symmetrical voltage handling.
According to another embodiment, the peripheral structure according to the invention is implemented in a ‘smart-power’ type monolithic power integration mode, for which insulating techniques are injected into the substrate in order to differentiate regions allocated to (high voltage) power functions and regions sustaining circuits for controlling and processing the signals and the (low voltage) information.
The junctions define main boxes with the second doping sign and each delineated by the corresponding junction and by the adjoining face.
Preferably, these main boxes are peripheral.
In a preferred embodiment, the substrate is of N-type and the main box and the insulating box are of P-type. The junction is then adjacent to the front face.
In another embodiment, the substrate is of P-type and the main box and the insulating box are of N-type, whereas the junction is then adjoining to the rear face.
Preferably, the insulating box is little doped and the boxes are highly doped.
In a preferred embodiment, the insulating box is made of a highly doped insulating vertical wall and the component comprises at least one small dose implantation zone of the second doping type, adjacent to that wall and to one of the front and rear faces and a
Austin Patrick
Breil Marie
Causse Olivier
Jalade Jean
Laur Jean-Pierre
Centre National de la Recherche Scientifique
Farahani Dana
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