Peripheral memory interface controller as a cache for a large da

Details Peripheral memory interface controller as a cache for a large da Peripheral memory interface controller as a cache for a large da

1991-08-05

1995-08-29

Eng, David Y.

Boots, shoes, and leggings

36492692, 36492693, 3649642, 3642383, 3642384, 3642434, G06F 1316

Patent

active

054468442

ABSTRACT:
An interface controller coupled between the main memory system and the I/O system of a large data processing system which controller is able to receive memory access requests from a number of different peripheral devices. The memory interface controller is provided with a data array for holding a number of data words fetched from memory which data array in turn is addressed by the output of an address array. The address array is an associative memory that can associate a given main memory address, of data in the data array, with a data array address containing data stored in main memory at that main memory address so that actual main memory access need not be required.

REFERENCES:
patent: 3588829 (1971-06-01), Boland
patent: 3789365 (1974-01-01), Jen
patent: 4056845 (1977-11-01), Churchill
patent: 4186438 (1980-01-01), Benson et al.
patent: 4499539 (1985-02-01), Vosacek
patent: 4736293 (1988-04-01), Patrick

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