Peripheral controller with paged data buffer management

Details Peripheral controller with paged data buffer management Peripheral controller with paged data buffer management

1989-01-10

1989-12-19

Smith, Jerry

Boots, shoes, and leggings

3649260, 3649277, 3649571, G06F 1310

Patent

active

048887277

ABSTRACT:
A controller controls data transfers between a data processing system bus and peripheral devices. In the controller, data buffers are divided into page frames. Paging circuitry provides for allocation and deallocation of pages to and from the data buffer. Included in the page circuitry is a paging RAM. The paging RAM and other paging circuitry components allow contiguously addressed pages of data to be stored in noncontiguous locations in the data buffer. There may be more than one data buffer and these data buffers may be exclusively seized by microprocessors in the controller via seizing logic.

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"Standard Printer or I/O Adapter Control Method and Apparatus", D. O. Hays et al., IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, pp. 269-271.
"The Handbook of Computers and Computing", Ivan Flores, 1984, pp. 224-227.

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