Peripheral bus transaction routing using primary and node ID...

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Alternate path routing

Reexamination Certificate

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Details

C709S238000, C709S240000, C709S241000, C710S038000, C710S305000, C710S306000, C710S316000, C710S317000

Reexamination Certificate

active

07380018

ABSTRACT:
A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources and a node ID register. The primary routing resources are programmable with a plurality of address ranges. The processing device is operable to determine a routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination address of the peripheral bus transaction and primary routing resources contents. The node ID register is programmable with a plurality of override indications. The processing device is operable to determine an override routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination node ID of the peripheral bus transaction and node ID register contents.

REFERENCES:
patent: 5835710 (1998-11-01), Nagami et al.
patent: 6598080 (2003-07-01), Nagami et al.
patent: 7039709 (2006-05-01), Beadle et al.
patent: 2001/0026550 (2001-10-01), Kobayashi
patent: 2003/0005152 (2003-01-01), Diwan et al.

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