Peripheral apparatus for image memories

Details Peripheral apparatus for image memories Peripheral apparatus for image memories

1985-09-05

1988-08-23

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340723, 340744, 340789, G09G 116

Patent

active

047664312

ABSTRACT:
A peripheral apparatus for image memories can communicate image data with a memory assembly having n blocks of a standard-type DRAM, whether the DRAM is for a page mode or for a nibble mode type operation. The apparatus comprises a read data processing unit sending the data of a selected one among n pixels read from the DRAM blocks in parallel to an external image/graphics processor, a write data processing unit modifying the image data taken thereinto and writing the modified data into the DRAM blocks, a feedback data processing unit writing the image data now on displaying into the DRAM blocks after a desired processing again, a display data processing unit sending the data read from the DRAM blocks to a monitor for display and to the external processor for the feedback processing, and a control unit furnishing control signals to those processing units in response to instructions from the external processer.

REFERENCES:
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patent: 4396295 (1983-08-01), Ishikawa
patent: 4445114 (1984-04-01), Stubben
patent: 4562435 (1985-12-01), McDonongh et al.
patent: 4575717 (1986-03-01), Fedele
patent: 4580135 (1986-04-01), Kummer et al.
"Color-Graphics Controller Chip Set Reduces Parts Count, Incorporates Microcomputer", Electronics, Apr. 19, 1984, pp. 166-168.

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