Boots – shoes – and leggings
Patent
1996-12-11
1998-06-02
Elmore, Reba I.
Boots, shoes, and leggings
368120, 395555, G06F 102
Patent
active
057611009
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a period generator used in a semiconductor device testing apparatus for generating a pulse having a test period which is set, i.e., a pulse having a test pattern generating period, and more particularly, to a period generator for generating such pulses by generating a pulse using a counter with respect to an integer part of the set period and delaying the generated pulse by a decimal fraction part (part lower than decimal point) of the set Period in a delay circuit.
BACKGROUND ART
FIG. 1 shows a conventional period generator of this type. An address from a pattern generator 11 is applied to a period value memory 12 in which various period values are previously set at corresponding addresses and a set period value specified by the address is read out from the period value memory 12 at every enabling period of the pattern generator 11. An integer part I the unit of which is one clock period is set to a coincidence detection counter 13 and a fraction part F of the set period value is applied to one input of an adder 14. The coincidence detection counter 13 counts the number of clocks from a clock generator 15 and supplies an output to a delay circuit 16 when the count of clock coincides with the set integer I. The fraction part F from the period value memory 12 is added to the output of a flip-flop 17 by the adder 14 and the summed result is latched to the flip-flop 17 by the clock from the clock generator 15 and the enabling signal. A carry output of the adder 14 is latched to a flip-flop 18 by the clock and the enabling signal. The fraction part read out from the period value memory 12 is a value less than the clock period T and when the summed result of the adder 14 becomes equal to or greater than the period T, a carry output is generated. When the carry output is generated, an output of the coincidence detection counter 13 is delayed by one clock period T in a delay circuit 16 and is supplied to a variable delay element 19. When the carry output is not generated, the output of the coincidence detection counter 13 passes through the delay circuit 16 without being delayed and is supplied to the variable delay element 19. An output of the delay circuit 16 is supplied to the pattern generator 11 as a next period generation trigger. The output of the flip-flop 17 is set in the delay element 19 as a delay amount.
An output of the delay element 19 is supplied to a delayed waveform generator 22 as an output of the period generator 21. This delayed waveform generator 22 generates a pattern delayed by the delay amount (phase) set by the pattern generator 11 and having a set waveform based on the pulses from the period generator 21 as the reference. This pattern is applied to a pin terminal of an IC under test 24 via a driver 23. Incidentally, the delay circuit 16 is, for example as shown in the figure, arranged such that the output of the coincidence detection counter 13 is supplied to gates 16a and 16b, the output of the flip-flop 18 is supplied to the gate 16b, the inverted output of the flip-flop 18 is supplied to the gate 16a, the output of the gate 16b is supplied to a flip-flop 16c, and the output of the flip-flop 16c and the output of the gate 16a are supplied to an OR gate 16d. The pattern generator 11 is operated by the clock of the clock generator 15. The change of the output data i.e., the address of the period generator changes for every enabling. The delayed waveform generator 22 is also operated by the clock of the clock generator 15. The read timing of the period value memory 12 is determined by the clock of the clock generator 15. Each of the flip-flops 17, 18 and 16c is given at its enabling terminal an output pulse RA of the delay circuit 16 and takes in an input by the clock of the clock generator 15 during the output pulse RA is present.
If a set period T.sub.S is, for example, 2.25T, the integer I=2 from the period value memory 12 is set in the coincidence counter 13 and the fraction F=0.25 is supplied to the adder 14. As shown in FIG. 2, wh
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patent: 5274796 (1993-12-01), Conney
patent: 5459419 (1995-10-01), Hatakenaka
patent: 5592659 (1997-01-01), Toyama et al.
Itoh Masayuki
Tsuruki Yasutaka
Advantest Corporation
Elmore Reba I.
Moise Emmanuel L.
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