Performance optimizing compiler for building a compiled SRAM

Details Performance optimizing compiler for building a compiled SRAM Performance optimizing compiler for building a compiled SRAM

1999-01-04

1999-12-14

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365154, 365156, G11C 800, G11C 1100

Patent

active

060026332

ABSTRACT:
A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.

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