Performance optimized approach for efficient downsampling...

Details Performance optimized approach for efficient downsampling... Performance optimized approach for efficient downsampling...

2006-10-24

2006-10-24

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S523000

Reexamination Certificate

active

07127482

ABSTRACT:
An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC ( multiply-add-accumulator) kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC (add-multiply-add-accumulator) kernals (described in detail below), when operating in a downsampling mode.

REFERENCES:
patent: 5594679 (1997-01-01), Iwata
patent: 6327602 (2001-12-01), Kim
patent: 6526430 (2003-02-01), Hung et al.

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