Performance invarient execution unit for non-communicative instr

Details Performance invarient execution unit for non-communicative instr Performance invarient execution unit for non-communicative instr

1976-12-29

1978-04-18

Chapnick, Melvin B.

Boots, shoes, and leggings

364716, G06F 738, G06F 918

Patent

active

040854507

ABSTRACT:
An arithmetic processor includes an input buffer and a result buffer connected through a pair of multiplexers to a pair of working registers feeding three parallel execution units. Operands stored in the buffers are selected for processing by addressing the buffers and multiplexers. Instruction overlapping is provided whereby operands of one instruction are read in parallel with the execution of the previous instruction. Further, reverse operations are processed identically as forward or normal operations except for addressing thereby achieving invarience of performance under non-communicative instructions.

REFERENCES:
patent: 3252149 (1966-05-01), Weida et al.
patent: 3564226 (1971-02-01), Seligman
patent: 3689895 (1972-09-01), Kitamura
patent: 3840861 (1974-10-01), Amdahl et al.
patent: 3887799 (1975-06-01), Lindgren
patent: 3932845 (1976-01-01), Beriot
patent: 3953833 (1976-04-01), Shapiro
D. Sofer et al., "Parallel Pipeline Organization of Execution Unit", in IBM Tech. Discl. Bull., vol. 14, No. 10, Mar. 1972, pp. 2930-2933.

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