Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Patent
1997-06-13
2000-05-09
Teska, Kevin
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
702186, 703 21, G06F 1750
Patent
active
060598352
ABSTRACT:
A processor performance evaluation system and method provides a method of model decomposition and trace attribution by first decomposing a full pipelined model of the entire system into a main model and one or more additional sub-models, such that it is possible to build fast trace-driven non-pipelined simulation models for the sub-models to compute specific metrics or values, which would be required during full-model, pipeline simulation. The main model is a fully pipelined model of the entire system; however, the simulation work required for the sub-units characterized by the sub-models is not coded into the simulation engine. Instead, the necessary values are provided from encoded fields within the input trace.
REFERENCES:
patent: 4901260 (1990-02-01), Lubachevsky
patent: 5303166 (1994-04-01), Amalfitano et al.
patent: 5371689 (1994-12-01), Tatsuma
patent: 5548539 (1996-08-01), Vlach et al.
patent: 5615357 (1997-03-01), Ball
patent: 5671402 (1997-09-01), Nasu et al.
patent: 5696942 (1997-12-01), Palnitkar et al.
patent: 5752002 (1998-05-01), Naidu et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5848262 (1998-12-01), Burch
S. Surya et al., Architectural performance verification: PowerPC processors, Computer Design, 1994, VLSI in Computers and Processors, ICCD '94, IEEE Int'l Conference, pp. 344-347.
P. Bose, Architectural Timing Verification and Test for Super Scalar Processors, Fault-Tolerant Computing, 1994, FTCS-24, Digest of Papers, 24th Int'l Symposium, pp. 256-265.
Iyengar et al., Representative Traces for Processor Models with Infinite Cache, High-Performance Computer Architecture, 1996, 2nd Int'l Symposium, pp. 62-72.
England Anthony V. S.
Frejd Russell W.
International Business Machines - Corporation
Kordzik Kelly K.
Teska Kevin
LandOfFree
Performance evaluation of processor operation using trace pre-pr does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Performance evaluation of processor operation using trace pre-pr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Performance evaluation of processor operation using trace pre-pr will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1060223