Performance enhancement for load multiple register instruction

Details Performance enhancement for load multiple register instruction Performance enhancement for load multiple register instruction

1993-02-02

1995-05-16

Harvey, Jack B.

395775, G06F 938

Patent

active

054169119

ABSTRACT:
In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event that a next sequential instruction requires the contents of one of the registers in the subset, the number of the required register is compared with the incremented number and the decoding phase of the next instruction is allowed to proceed when the required register has been loaded as indicated by the incremented number. The identity of the highest numbered and the next to highest numbered registers loaded by the LMR instruction are recorded in a target register and an exclusive or-circuit is provided to determine whether the total number of registers loaded by the LMR instruction is an even number or an odd number. The output of the exclusive or-circuit is used to determine whether the next-to-highest numbered register is by-passable for use in the operand fetch phase of the next instruction prior to completion of the last execution cycle of the LMR instruction.

REFERENCES:
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Losq, J. J., "Address Generate Interlock Memory Buffer", IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982.
Nair, R., et al., "Efficient Handling of Load Multiple Instruction", IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982.
Rao, G. S., "Use of Load Bypass on Load Multiple Instruction to Reduce Address Generation Interlock Delays", IBM Technical Disclosure Bulletin, vol. 25, No. 5, Oct. 1982.

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