Performance driven multi-valued variable supply voltage...

Details Performance driven multi-valued variable supply voltage... Performance driven multi-valued variable supply voltage...

1999-12-28

2001-05-01

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S565000, 36

Reexamination Certificate

active

06225858

ABSTRACT:

TECHNICAL FIELD
The present invention relates to very large scale integrated (VLSI) circuit design, and more particularly, to a design method that reduces power consumption using plural supply voltage levels.
BACKGROUND OF THE INVENTION
One driving factor behind the push for low power design is the growing class of personal computing and communications devices that demand complex functions at high speed and low power to enable them to be supplied by existing power supplies. Another driving fact is that excessive power consumption has become a limiting factor in integrating more transistors on a single chip. Unless power consumption is dramatically reduced, the resulting heat will limit the feasible packing and performance of VLSI circuits and systems.
One method of reducing power consumption that has been recently proposed is to employ multiple supply voltages. The authors of Chang, J. M. and Pedram, M., “Energy Minimization Using Multiple Supply Voltages,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, December 1997 (“Chang”) describe a scheduling technique that assigns each operation in a data flow graph (DFG) to one of a fixed set of different supply voltages in order to minimize power consumption while meeting a predefined set of timing or throughput (for pipelined data paths) constraints. This technique starts from a high level description of the DFG and its output is a mapping of the optimized DFG onto a set of register transfer level (RTL) or data path operators (adders, multipliers, etc.) that have been previously characterized so as to get the power-timing tradeoff curves. In that sense the approach certainly belongs to the class of behavioral synthesis algorithms, and hence does not address the key issues of how to provide the multiple supply voltage rails on the chip with significantly penalizing the available routing resources.
A second approach is discussed in Kuroda, T. et al., “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998 (“Kuroda”). The approach in Kuroda is based on generating a mockup of the critical path of the design (actually two different replicas of the critical path, respectively 3% faster and slower). A built-in suite of test data are then transferred through the critical path mockups between register pairs that are clocked with the main clock of the system, and the output is compared with the output of a directly connected pair of registers. The result is used to feed a counter and eventually a voltage regulator that generates the supply voltage for the actual chip. Although the supply voltage is adaptively regulated to settle at its optimal (lowest) value V
DD
* using a local feedback loop, only one supply voltage is employed. As a result, a large portion of the system may still be fed with a supply voltage in excess of that required for complete operation within a clock cycle.
A third approach is discussed in Usami, K et al., “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, March 1998 (“Usami”). The technique in Usami applies a multiple supply voltage scheme to the synthesis, placement, and routing of RTL blocks. The authors in Usami assume that two different levels of supply voltage are available on the chip: V
DD
H
and V
DD
L
. During the technology mapping phase, each cell of a block is supplied at whichever one of the two different supply voltage levels minimizes the number of level shifters (required to convert from cells supplied with V
DD
L
to cells supplied with V
DD
H
. As in Chang, this approach is geared toward the front end of the design process, and thus, must employ an oversimplified model of the timing and power consumed by the cells. Also, because cells within the same hierarchical block can be assigned to different supply voltages, routing resources are severely penalized because of the other tracks that are necessary to distribute the extra supply rail. In addition, only two different supply voltages (V
DD
H
and V
DD
L
) are considered.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a method of reducing power consumption of an electric circuit having a primary supply voltage and first and second circuit blocks. The method includes determining for the first circuit block an operation time for a first critical path of the first circuit block and determining for the second circuit block an operation time of a second critical path of the second circuit block. From those operation times, the method determines that the operation time of the first critical path is faster than the operation time of the second critical path. The method then creates a first supply voltage for the first circuit block that is less than the primary supply voltage in response to determining that the operation time of the first critical path is faster than the operation time of the second critical path.
An embodiment of the invention is also directed to an electric circuit being supplied by a primary supply voltage and comprising a first circuit block having a first critical path and a second circuit block having a second critical path supplied by the primary supplied voltage. The electric circuit also includes a voltage regulator having an input coupled to the primary supply voltage and an output coupled to the first circuit block, the voltage regulator being structured to produce at the output a first supply voltage from the primary supply voltage, the first supply voltage being at a level less than the primary supply voltage and at a level that drives the first circuit block such that the first critical path operates at a speed approximately equal to a speed in which the second critical path operates.


REFERENCES:
patent: 5612892 (1997-03-01), Almulla
patent: 5-299624 (1993-11-01), None
patent: 9-270701 (1997-10-01), None
Chang and Pedram, “Energy Minimization Using Multiple Supply Voltages,”IEEE Transactions on a Very Large Scale Integration (VLSI) Systems5(4):436-443, 1997.
Kuroda et al., “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,”IEEE Journal of Solid-State Circuits, 33(3):454-461, Mar. 1998.
Usami and Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design,” Proceedings of the International Symposium on Low Power Design, pp. 3-8, Apr. 23, 1995.
Usami et al., “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,”IEEE Journal of Solid-State Circuits33(3):463-471, 1998.

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