Per-wafer method for globally stressing gate oxide during device

Details Per-wafer method for globally stressing gate oxide during device Per-wafer method for globally stressing gate oxide during device

1993-08-27

1995-02-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437170, 324 715, G01R 3126

Patent

active

053915020

ABSTRACT:
Gate oxide on a semiconductor wafer is effectively stressed on a per-wafer basis during fabrication. Because it was effectively stressed, gross testing the gate oxide after device fabrication provides a good indication whether a completed MOS device will be subject to infant mortality. After the gate oxide is formed, a source of overvoltage may be coupled between the raw oxide and the underside of the wafer, to accelerate stress due to defects in the oxide. Alternatively, the oxide may be stressed after deposition of the gate material by coupling a source of overvoltage directly to the gate material and to a probe on the underside of the wafer. The oxide may also be stressed after patterning and definition of the gate material by coupling a source of over-voltage to all of the gates simultaneously, preferably using a mercury probe, plasma or a conductive conforming membrane, and to a probe on the underside of the wafer. The overvoltage is sufficiently large to stress defect-containing oxide, but not to breakdown good oxide. After stress, prior art procedures to complete fabrication, post-fabrication burn-in and testing may be carried out. Because the present invention effectively stresses 100% of the gate oxide, fabricated ICs containing MOS devices whose oxide has defects will generally not pass GO/NO GO post-fabrication testing. In this manner, ICs likely to fail due to infant mortality are identified during post-fabrication testing and discarded.

REFERENCES:
patent: 3422528 (1969-01-01), Okumura
patent: 4360964 (1982-11-01), Gilly et al.
patent: 4760032 (1988-07-01), Turner
patent: 4975381 (1990-12-01), Taka et al.

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