Per pin circuit test system having N-bit pin interface providing

Details Per pin circuit test system having N-bit pin interface providing Per pin circuit test system having N-bit pin interface providing

1992-03-05

1995-01-10

Beausoliel, Jr., Robert W.

Excavating

371 251, G01R 3128, G06F 1100

Patent

active

053814215

ABSTRACT:
A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2.sup.M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.

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