Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2003-04-30
2004-11-02
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06812878
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to circuits, and more particularly to a digital-to-analog converter.
BACKGROUND OF THE INVENTION
Digital-to-analog converters (DACs) are circuits that receive digital inputs and produce analog outputs that are analog equivalents of the digital inputs in the form of currents or voltages. A typical DAC includes an encoder, a number of analog output elements and a summing circuit. The encoder receives a digital input, which is a digital value represented by a number of binary data bits, and then encodes the binary data bits into suitable drive signals to selectively activate the analog output elements. In response to the drive signals, the activated analog output elements generate partial analog signals. These partial analog signals are then combined by the summing circuit to produce an analog output, which is an analog representation of the digital input.
A problem that often arises during the operation of a DAC is the appearance of output errors called “glitches”, which are mainly caused by mistiming of the partial analog signals at the output of the DAC. These glitches do not affect the final, settled value of the analog output for each digital input, and appear only during the transition from one digital input to the next. Therefore, the glitches corrupt the spectral content of the output signal, which presents an important concern for high-speed applications since the glitches can be misinterpreted as analog outputs.
One source of mistiming is different arrival times of the data bits of a digital input at the input of the encoder. However, this mistiming source can be easily minimized by using latches at the input of the encoder to synchronize the data bits. Another source of mistiming is differential logic delay between the input of the encoder and the output of the encoder. Again, this mistiming source can be minimized by adding latches at the output of the encoder with a carefully controlled clock. Still another source of mistiming is mismatch of path lengths between the encoder and the output analog elements and/or mismatch of path lengths between the output analog elements and the output of the DAC through the summing circuit. This last source of mistiming can be minimized by adding a switch between the summing circuit and the output of the DAC. The switch is used to pass the analog signal to the output only after the signal has settled to a final value. Thus, the portion of the analog signal with glitches can be blocked by to the use of the switch. This technique returns the output waveform to zero or some reference value during the problematic time, and thus, is commonly referred to as “Return to Zero” or RZ.
Using the RZ technique, the mismatched delays before the summing unit no longer affect the high-speed performance of the DAC, and the signal integrity becomes limited primarily by the linearity of the switch and the purity of a resampling clock used to operate the switch. Between these two limiting factors, the linearity of the switch is the main limiting factor. Switch nonlinearity can be due to the series resistance of the switch, which may have a nonlinear function with respect to the current passing through the switch. Furthermore, the switch nonlinearity may be due to other nonlinear parasitics, such as capacitance, which vary with current levels.
In view of this consideration, there is a need for a DAC and method for converting digital inputs into analog outputs such that glitches in the output signal are reduced or eliminated without introducing switch nonlinearity into the output signal.
SUMMARY OF THE INVENTION
A digital-to-analog converter (DAC) and method for converting digital inputs into analog outputs utilizes resampling switches to regulate the transmission of partial analog signals between analog output elements and a summing circuit to reduce or eliminate “glitches” in the output signal. Each resampling switch may be individually connected to an analog output element to handle a fixed partial analog signal, e.g., a fixed current, generated by that analog output element. Consequently, the resampling switches can be used to reduce or eliminate the glitches in the output signal without introducing switch nonlinearity into the output signal by simultaneously transmitting the partial analog signals to the summing circuit using the resampling switches.
A DAC in accordance with an embodiment of the invention includes a number of analog output elements, a number of switches and a summing circuit. The analog output elements are configured to selectively generate partial analog signals in response to a digital input. The summing circuit is configured to combine the partial analog signals to produce an analog output, which is an analog representation of the digital input. The switches are located between the analog output elements and the summing circuit to regulate the transmission of the partial analog signals between the analog output elements and the summing circuit. Each switch may be connected to a distinct analog output element to transmit the partial analog signal generated by that analog output element to the summing circuit.
A method for converting digital inputs into analog outputs in accordance with an embodiment of the invention includes receiving a digital input, generating partial analog signals in response to the digital input, regulating the transmission of the partial analog signals, and receiving and combining the partial analog signals to produce an analog output, which is an analog representation of the digital input.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrated by way of example of the principles of the invention.
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patent: 5793320 (1998-08-01), Keum et al.
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Alexander R. Bugeja, Bang-Sup Song, Patrick L. Rakers and Steven F. Gillig; “A 14b 100M Sample/s CMOS DAC Designed for Spectral Performance”, pp. 148-149, ISSCC 1999 Digest of Technical Papers, Feb. 1999.
Jewett Robert E.
Liu Jacky Kin Chi
Agilent Technologie,s Inc.
Jean-Pierre Peguy
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