Peer-to-peer parallel processing graphics accelerator

Details Peer-to-peer parallel processing graphics accelerator Peer-to-peer parallel processing graphics accelerator

1996-12-05

1999-06-29

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345506, 345520, G06F 1580

Patent

active

059175028

ABSTRACT:
A graphics processing accelerator has a plurality of digital signal processors that each have an output, and an input in communication with a request bus. The digital signal processors are arranged in a peer-to-peer configuration to process, on a cyclical basis, each of a successive series of graphics requests received over a request bus. The graphics processing accelerator also may have a sequencer in communication with each digital signal processor output for ordering graphics requests processed by the digital signal processors.

REFERENCES:
patent: 5394524 (1995-02-01), DiNicola et al.
patent: 5446479 (1995-08-01), Thompson et al.
patent: 5557734 (1996-09-01), Wilson
IEEE Computer Society Press, "A Multiprocessor System Utilizing Enhanced DSP'S for Image Processing" by Ueda et al. pp. 611-620, May 25-27, 1988.
Proceedings of the 5th International Conference on Image Analysis and Processing, "A Dataflow Image Processing System TIP-4" by Y. Fujita et al, Sep. 20-22, 1989.

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