Peak voltage detector circuit and binarizing circuit...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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C320S148000, C324S076160

Reexamination Certificate

active

08008948

ABSTRACT:
A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

REFERENCES:
patent: 5555452 (1996-09-01), Callaway, Jr. et al.
patent: 5598086 (1997-01-01), Somerville
patent: 5729130 (1998-03-01), Moody et al.
patent: U-53-42652 (1978-04-01), None
patent: A-60-102568 (1985-06-01), None
patent: A-60-114771 (1985-06-01), None
patent: A-2-054177 (1990-02-01), None
patent: A-6-174756 (1994-06-01), None
patent: A-10-135800 (1998-05-01), None
patent: A-2006-252647 (2006-09-01), None
Notice of Reasons for Refusal mailed on Oct. 19, 2010 issued from the Japanese Patent Office in the corresponding Japanese patent application No. 2007-178498 (with English translation).

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