Peak shift correction circuit and magnetic storage medium...

Dynamic magnetic information storage or retrieval – General processing of a digital signal – Pulse crowding correction

Reexamination Certificate

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Details

C360S046000, C360S051000, C360S053000

Reexamination Certificate

active

06633443

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a peak shift correction circuit for correcting a peak shift for a peak detection signal from a playback signal provided from a magnetic storage medium such as a magnetic tape or a floppy disk and to a magnetic storage medium playback apparatus using the circuit.
2. Description of the Related Art
Currently, with a floppy disk unit or a data streamer unit for the backup of data stored in a hard disk unit, digital data are recorded on a storage medium such as a floppy disk or a cartridge tape with a format configuration as shown in FIG.
7
.
In general, on the magnetic storage media, one or more segments are formed onto each track, and the configuration of one segment on the magnetic storage media is shown in FIG.
7
A. One segment is comprised of a header, sectors, and a gap. The header is an area which is used in order to make the data recorded in the sectors are read appropriately. The sectors are areas where the data are recorded. The gap is a blank which separates the next segment.
The header is constructed as shown in
FIG. 7B
, where the “GAP” represents a blank area and the “SYNC” represents a synchronizing signal. The “IAM” represents an index address mark which indicates the header.
The sector is comprised of an ID portion and a data portion as shown in FIG.
7
C. An attribute for the sector is recorded in the ID portion, and data are recorded in the data portion. The “GAP” represents a blank area, and the “SYNC” represents a synchronizing signal. The “IDAM” is an ID address mark which indicates the ID portion, and ID information such as a sector number and the length of the data are recorded in the “ID information” area. The “CRC” represents a cyclic code which is used for error detection. The “DAM” in the data portion represents a data address mark which indicates the data portion, and data are recorded in the “DATA” area.
When a data signal is recorded on the magnetic storage medium in the format configuration, the data signal is modulated by a FM method or a MFM method in order to be recorded on the magnetic storage medium.
For one bit of the data signal, the signal is generated in a unit which is called a bit cell. In the FM method, a clock pulse is recorded at the head of each bit cell, and a data pulse is recorded in the middle of each bit cell. In the MFM method, the data pulse is recorded in the middle of each bit cell, and the clock pulse is recorded at the head of the relevant bit cell only when no data are recorded (the data is “0”) in the current and present bit cells.
FIG. 8
shows data signals modulated by the FM and MFM methods. With the FM method, the data signal DT shown in
FIG. 8A
is converted into a recording signal FWS shown in
FIG. 8B
, where the reference character “C” on the recording signal FWS represents the clock pulse and the reference character “D” represents the data pulse. With the MFM method, the data signal DT is converted into a recording signal MWS shown in
FIG. 8C
, where the reference character “C” on the recording signal FWS also represents the clock pulse and the reference character “D” also represents the data pulse.
With the MFM method, when the time intervals between the bit cells of the recording signal MWS shown in
FIG. 8C
are shortened by half, the time intervals are equal to those in the FM method, and it is possible to record the data at a density level double that of the FM method. Accordingly, when the digital data are recorded in the high density, the data are generally recorded using the MFM method.
FIG. 9
shows a construction of a conventional magnetic recording storage medium playback apparatus which plays back the data signal from a magnetic storage medium and provides a playback signal. The data signal is recorded at a transmission speed of, for example, 1 megabit/second (the interval between the bit cells=1 &mgr;s).
A recording signal WD into which the data signal DT is modulated, is supplied to a flip-flop
1
. The flip-flop
1
generates a recording current control signal RC in which the logic level is inverted, synchronized with a rise of the recording signal WD. The recording current control signal RC is supplied to a write amplifier
2
. The write amplifier
2
generates a recording current WI based on the recording current control signal RC, which is then supplied to a magnetic head
3
. The magnetic head
3
generates a residual flux based on the recording current WI which is recorded on a magnetic storage medium (not shown).
When the magnetic storage medium on which the data signal DT is recorded, is played back, the magnetic storage medium (not shown) is played back using the magnetic head
3
, so that a playback signal RS is outputted from a pre-amplifier
4
. The playback signal RS is supplied to a differentiator
5
, an integrator
6
, and a direct current signal generator
7
.
The differentiator
5
differentiates the playback signal RS, generating a differentiated signal DRS. In order to correct a peak shift described below, the integrator
6
integrates the playback signal RS in order to provide an integrated signal IRS, and the direct current signal generator
7
generates a direct current signal DCR based on the playback signal RS.
The integrated signal IRS and the direct current signal DCR are supplied to an adder
8
, which provides an added signal MID and such signal is provided and is supplied to a subtractor
9
. The subtractor
9
, upon receiving the differentiated signal DRS from the differentiator
5
, subtracts the added signal MID from the differentiated signal DRS to produce a synthesized signal MRS. The synthesized signal MRS is supplied to a zero-volt comparator
10
.
The zero-volt comparator
10
outputs the comparison signal CRS at a high level “H” when the synthesized signal MRS is above 0 volts, and outputs the comparison signal CRS at a low level “L” when the synthesized signal MRS is below 0 volts. The comparison signal CRS is supplied to a pulse shaping circuit
11
.
The pulse shaping circuit
11
generates a pulse signal synchronized with an inverted signal level of the comparison signal CRS and provides a read signal RD.
Referring to
FIG. 10
, the operation of the magnetic storage medium playback apparatus is described below.
FIG. 10A
shows the recording signal WD. At point t
1
, when the recording signal WD is increased to the high level H, the recording current control signal RC outputted from the flip-flop
1
shown in
FIG. 10B
, is inverted from the high level H into the low level L. Based on the recording current control signal RC, the recording current WI at “−I” is supplied to the magnetic head
3
as shown in
FIG. 10C
so that the signal can be recorded on the magnetic storage medium.
At point t
2
after one bit cell period has passed, when the recording signal WD is increased to the high level H, the recording current control signal RC is inverted into the high level H, and the recording current WI at “+I” is supplied to the magnetic head
3
so that the signal is recorded on the magnetic storage medium.
Thereafter, the recording current control signal RC is inverted, synchronized with the inversion of the recording signal WD, and the recording current WI at “−I” or “+I” is supplied to the magnetic head
3
so that the signal can be recorded on the magnetic storage medium.
When the signal recorded on the magnetic storage medium is played back with the magnetic head
3
, the playback signal RS shown in
FIG. 10D
is outputted from the pre-amplifier
4
. For example, when a datum at the position on the magnetic storage medium at point t
1
is played back, the playback signal RS at point t
5
is outputted, and when a datum at the position at point t
2
, the playback signal RS at point t
6
is outputted.
The playback signal RS is supplied to the differentiator
5
, where the differentiated signal DRS shown in
FIG. 10E
is generated. The adder
8
adds the integrated signal IRS from the integrator
6
to the direct current signal DCR from the direct cu

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