Peak-hold circuit and signal strength indicator using the...

Telecommunications – Receiver or analog modulated signal frequency converter – Measuring or testing of receiver

Reexamination Certificate

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Details

C327S050000

Reexamination Certificate

active

07853226

ABSTRACT:
A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

REFERENCES:
patent: 4216502 (1980-08-01), Fox
patent: 5521542 (1996-05-01), Kimura
patent: 6311049 (2001-10-01), Yoshizawa
patent: 2003-163556 (2003-06-01), None

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