Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-11-28
2002-12-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S058000, C327S095000, C327S094000
Reexamination Certificate
active
06498517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a peak hold circuit, and particularly relates to a current mode peak hold circuit wherein output current corresponding to the peak value of input current can be obtained even for input currents with little change in magnitude, at essentially higher speeds.
2. Description of the Related Art
An example of a conventionally-known peak hold circuit wherein output voltage corresponding to peak values of input voltage can be obtained is shown in FIG.
25
. The voltage of the non-inverting input terminals of an operational amplifier
2502
(equal to the voltage VH held by a capacitor
2507
) is initially equal to the voltage VIN
1
of the non-inverting input terminals of an operational amplifier
2501
.
Thus, the voltage of the output terminal of the operational amplifier
2502
, the voltage of the inversion input terminal of the operational amplifier
2501
, and the voltage of the output terminal of the operational amplifier
2501
are VH which is VIN
1
, the voltage at both ends of the diodes
2503
and
2504
are zero, with the diodes
2503
and
2504
being in a non-conducting state.
In this state, even in the event that the voltage of the input terminal
2508
rises and reaches VIN
2
, the diode
2503
is in a non-conducting state, so the output voltage of the operational amplifier
2501
rises greatly regardless of the negative feedback. Then, when forward voltage is applied to the diode
2504
an the diode
2504
is in a conducting state, the capacitor
2507
is charged, the voltage at both ends of the capacitor
2507
rises, and in the same manner, the voltage of the output terminal
2509
of the operational amplifier
2502
and the voltage of the inverted input terminals of the operational amplifier
2503
rise.
Then, at the point that the voltage at both ends of the capacitor
2507
is equal to the voltage VIN
2
of the output terminal
2509
of the operational amplifier
2501
, the diode
2504
enters a non-conducting state, and consequently, the voltage VIN
2
is held by the capacitor
2507
.
In the event that the voltage of the input terminals
2508
drops and changes from VIN
2
to VIN
3
in this state, while the output voltage of the operational amplifier
2501
drops, the voltage at both ends of the capacitor
2507
(i.e., the held voltage VH) is VIN
2
, so inverse voltage is applied to both ends of the diode
2504
, so the diode
2504
remains in a non-conducting state, and the held voltage VH remains unchanged at VIN
2
.
Thus, voltage corresponding to the peak value of he input voltage of the input terminals
2508
is output at the output terminal
2509
.
However, such voltage mode peak hold circuits are configured of multiple operational amplifiers, diodes, capacitors, and so forth, so the circuit tends to become large in size.
Also, the circuit is arranged so as to make input to the peak hold circuit shown in
FIG. 25
following converting the input current into voltage values with a current/voltage converting circuit, so there is a limit to how far the size of the circuit can be reduced, and the circuit has not been able to be reduced in size any further.
A known example of a peak hold circuit which has solved such problems is described in Japanese Patent Application No. 10-5449. This peak hold circuit is known as a current mode peak hold circuit, and has a configuration such as shown in FIG.
26
.
FIG. 26
will now be described. This current mode peak hold circuit is configured of P-MOS transistors
2601
and
2602
, an NPN transistor
2603
, and a PNP transistor
2607
. The gates of the P-MOS transistors
2601
and
2602
are connected in common, and the sources are connected to the electric power source VDD. The P-MOS transistor
2601
has the drain thereof connected to the terminal
2604
, and the NPN transistor
2602
has the drain thereof connected to the terminal
2606
. The collector of the NPN transistor
2603
is connected to the gates of the P-MOS transistor
2601
and
2602
connected in common, the emitter thereof is connected to the drain of the P-MOS transistor
2601
, and the base is connected to a reference potential VBIAS
1
. The emitter of the PNP transistor
2607
is connected to the drain of the P-MOS
26501
, the base the base is connected to a reference potential VBIAS
2
, and the collector is grounded.
The reference potential VBIAS
1
and the reference potential VBIAS
2
are lower than the voltage of the electric power source VDD but higher than the ground potential, are a potential such that the NPN transistor
2603
and the PNP transistor
2607
do not turn on simultaneously, and the difference potential between the reference potential VBIAS
1
and the reference potential VBIAS
2
is 0.7 V, for example.
In
FIG. 26
, V
4
(t) represents the absolute potential of the terminal
2604
at time t, iD
1
(t) represents the drain current of the P-MOS transistor
2601
at time t, iin(t) represents input current at time t, and iout(t) is output current at time t, with the direction of the arrows being the forward direction for each. Note that iout(t) matches the drain current of the P-MOS transistor
2602
.
(1) Let us say that the P-MOS transistor
2601
is operated at saturation range, and the drain current iD
1
(t) and input current iin(t) of the P-MOS transistor
2601
match. In this state, the potential of the terminal
2604
is generally the average potential of the two reference potentials VBIAS
1
and VBIAS
2
, the voltage between the base and emitter of the NPN transistor
2603
and PNP transistor
2607
are both around 0.35 V, and both the NPN transistor
2603
and PNP transistor
2607
are in the cut-off state.
In the event that the input current iin(t) increases over a period from time t
0
to time t
1
as shown in
FIG. 27A
for example, the relation between the drain current iD
1
(t) and input current iin(t) of the P-MOS transistor
2601
becomes that represented by iD
1
(t)<iin(t), and the voltage of the terminal
2604
drops.
The PNP transistor
2607
maintains the cut-off state, but at the point that the voltage of the terminal
2604
drops around 0.5 V as to the reference potential VBIAS
1
, the NPN transistor
2603
enters the forward activation range and begins to cause current to flow, and at the point that the voltage of the terminal
2604
drops around 0.7 V as to the reference potential VBIAS
1
, the NPN transistor
2603
turns on.
At the point that the NPN transistor
2603
turns on, the difference current between the input current and the drain current iD
1
(t) of the P-MOS transistor
2601
, i.e., iin(t)−iD
1
(t), flows from the node
2605
to the terminal
2604
via the NPN transistor
2603
, and the voltage of the node
2605
drops so that the input current iin(t) and the drain current iD
1
(t) of the P-MOS transistor
2601
are equal. The voltage drop of this node
2605
is generated by charge being extracted from the parasitic capacity between the gate sources of the P-MOS transistors
2601
and
2602
connected to the node
2605
, via the NPN transistor
2603
. At this time, the peak hold circuit shown in
FIG. 26
acts as a current mirror circuit, and output current proportionate to the input current is obtained (see FIG.
27
B).
(2) In the event that the increase of the input current iin(t) stops over a period from time t
1
to time t
2
as shown in
FIG. 27A
for example, iD
1
(t) =iin(t), and the NPN transistor
2603
and PNP transistor
2607
are both in the cut-off state, so the voltage of the terminal
2604
rises, and the voltage of the terminal
2604
settles down at around the average potential of the two reference potentials VBIAS
1
and VBIAS
2
. At this time, the node
2605
is in a high-impedance state, so the charge at time t
1
at the parasitic capacity between the gate sources of the P-MOS transistors
2601
and
2602
does not change.
On the other hand, the voltage between the gate sources of the P-MOS transistors
2601
and
2602
is maintained at VGS(t
1
), and output current iout(t) proportionate
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