Peak hold circuit

Details Peak hold circuit Peak hold circuit

1990-06-12

1992-07-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307353, 307362, 328151, H03K 5159, H03K 5153, H03K 500

Patent

active

051343134

ABSTRACT:
In a sampling mode, a servo signal sampling and holding switch (4.sub.a) and a reference voltage sampling and holding switch (30.sub.a) are turned off, so that transistors (Q.sub.7a, Q.sub.5a) are turned on. In response to on states of the transistors (Q.sub.7a, Q.sub.5a), capacities (C.sub.3a, C.sub.30a) are charged with the peak voltage (V.sub.ref +(1/2)V.sub.s) of a servo signal and a reference voltage (V.sub.ref), respectively. In a holding mode, the sampling and holding switches (4.sub.a, 30.sub.a) are turned on, so that the transistors (Q.sub.7a, Q.sub.5a) are turned off. the charging voltages (D, E) of the capacitors (C.sub.3a, C.sub.30a) are discharged through post-stage buffers (5.sub.a, 3.sub.a), so that they include offsets which are canceled through a subtractor (6.sub.a).

REFERENCES:
patent: 3820033 (1974-06-01), Iwata
patent: 3851260 (1974-11-01), Collin
patent: 4295099 (1981-10-01), Evans
patent: 4845382 (1989-07-01), Eouzan et al.

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