Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1997-06-27
2001-03-27
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S061000, C327S062000
Reexamination Certificate
active
06208173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a peak detector for detecting the magnitude of the peak of a signal applied to an input of the detector.
2. Description of Related Art
In many data systems it is desirable to get a rapid estimate of the amplitude in order to obtain slicing levels early in a signal burst, but producing a very sensitive and fast detector means that the noise bandwidth is large and that the signal amplitude can easily be over-estimated. Thus, there is a basic incompatibility of two requirements. That is, a rapid following of the peak to monitor the maximum amplitude of the signal is desirable but a slower response is required to prevent the occurrence of noise spikes from unduly affecting the detected peak value. One application of such a peak detector is in a data slicer, particularly for teletext signals. In this application a fast estimation of the amplitude of the signal is required in order to generate a data slicing level. This estimate is normally derived from the clock run-in signal which has a limited duration and hence the peak detector needs to be able to detect the peaks relatively quickly. If, however, there are noise spikes on the signal these are likely to generate incorrect data slicing levels if the peak detector reacts too quickly to them.
SUMMARY OF THE INVENTION
It is an object of the invention to enable the provision of a peak detector which quickly captures the peak value of the input signal but which does not react quickly to moderate amounts of noise on the signal.
The invention provides a peak detector for detecting the peak amplitude of an input signal, the peak detector comprising storage means for storing a value representing the currently detected peak amplitude, means for detecting whether the input signal amplitude exceeds the stored value, means for updating the stored value at a first (fast) rate if the input signal amplitude exceeds the stored value by more than a given value, and means for updating the stored value at a second (slower) rate if the input signal amplitude exceeds the stored value by less than the given value.
By this means the peak detector will follow a fast edge of an input signal until it reaches a value close to its peak value since under these circumstances the difference between the input signal and the stored value will be relatively large. As the input signal approaches its peak value the difference between the input signal and the stored value will decrease and when the given value is reached the updating of the stored value will take place at a slower rate. Thus, a very fast coarse estimate of the peak value is made up to a large fraction of the true peak level and after this level is reached the detector reacts more slowly to the further error input and hence does not react quickly to moderate amounts of noise on the signal.
In many applications the input signal will have a nominal peak value and in such a case the given value may lie between 10 and 30% of the nominal peak value of the input signal. The precise value of the given value may be a function of the particular application. The greater the proportion of the nominal peak value that is allocated to the given value the slower the actual following of the peak will be but the greater the noise margin will be. Consequently, the choice is between a rapid approach to the peak value and maximum immunity to noise.
The peak detector may comprise a differential pair of transistors, a capacitor, means for applying the input signal to the control electrode of the first transistor, means for connecting the capacitor between the control electrode of the second transistor and a first supply rail, means for charging the capacitor at a rate determined by the current conducted by the main current path of the second transistor and further charging means for providing a further charging current for the capacitor when the input signal voltage exceeds the voltage across the capacitor by more than the given value.
The further charging means may comprise a further transistor connected between a second supply rail and the capacitor, said further transistor being controlled to supply a charging current to the capacitor when the input signal voltage exceeds the voltage across the capacitor by a given amount.
The first transistor may have a constant current source load and may be further connected to the control electrode of the further transistor, the further transistor becoming conductive when the first transistor attempts to conduct a current greater than that produced by the constant current source.
A peak detector as set forth in the three preceding paragraphs provides an analog implementation of a peak detector according to the invention. The invention is, however, by no means restricted to analog implementations, although clearly the input signal may in most cases be an analog value.
In a partially digital implementation of a peak detector according to the invention, the storage means may comprise an accumulator, the means for updating the stored value at the first rate comprising means for adding a first number N to the accumulator and the means for updating the stored value at the second rate may comprise means for adding a second number M to the accumulator, where N is greater than M. M may be equal to 1.
Such a peak detector may comprise first and second comparators, means for feeding the input signal to first inputs of the first and second comparators, means for feeding the outputs of the accumulator to a second input of the second comparator, means for adding the given value to the output of the accumulator and feeding it to the second input of the first comparator, means for adding N to the accumulator when the input signal is greater than the signal at the second input of the first comparator and means for adding M to the accumulator when the input signal is greater than the signal at the second input to the second comparator and less than the signal at the second input of the first comparator.
The output of the accumulator may be fed to the first and second comparators via a digital to analog converter.
A further implementation of a peak detector comprises first and second digital to analog converters, the output of the accumulator being converted by the first digital to analog converter and fed to the second input of the second comparator, means for adding the given value to the output of the accumulator and applying the summed value to the second digital to analog converter and means for applying the output of the second digital to analog converter to the second input of the first comparator.
In this arrangement the offset between the second inputs of the first and second comparators is achieved by means of having two digital to analog converters and applying a digital offset to the accumulator output before applying it to one of the digital to analog converters. This gives the advantage that it is not necessary to produce an analog offset between the second inputs of the first and second comparators.
The peak detector may comprise a comparator having first and second inputs and first and second outputs, the first and second outputs having separate switching points dependent on different input voltage differences between the two inputs, the first output causing the number N to be added to the accumulator and the second output causing the number M to be added to the accumulator.
The comparator may comprise a transconductance stage having first and second current outputs, first and second trans-impedance stages each comprising an inverter and an offset generator comprising a current sink which sinks a fixed current from the second output of the transconductance stage.
This arrangement allows use of a single comparator and enables the offset to be generated in a simple manner occupying very little area on an integrated circuit.
The invention further provides a data slicer including a peak detector according to the invention. Such a data slicer may comprise means for feeding an input signal to a first positive pe
Rubin Steven S.
Tran Toan
U.S. Philips Corporation
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