Peak detector

Details Peak detector Peak detector

2001-05-21

2002-10-29

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Demand, excess, maximum or minimum

C324S1540PB

Reexamination Certificate

active

06472861

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89111022, filed Jun. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a signal detector. More particularly, the present invention relates to a peak detector having input signal triggering control and low frequency energy attenuation capability.
2. Description of Related Art
A peak detector is a device capable of measuring the peak value of a voltage signal. However, most peak detectors have no special faculties for distinguishing between high and low frequency signals. In real applications, the capacity of a peak detector to find the degree of signal attenuation in a local area network (LAN) or transmission medium such as cable or twisted pair is very important.
FIG. 1
is a circuit diagram of a conventional peak detector. As shown in
FIG. 1
, the conventional peak detector
10
comprises of a comparator
12
, an NMOS transistor
14
, a resistor
16
, a capacitor
18
and a current source
20
. The positive input terminal of comparator
12
is a terminal for receiving an input signal. The negative input terminal of comparator
12
is connected to a node point N
1
. The output terminal of comparator
12
is connected to the gate terminal of NMOS transistor
14
. The source terminal of NMOS transistor
14
is connected to the output terminal of current source
20
. The drain terminal of NMOS transistor
14
is connected to node point N
1
. One end of resistor
16
is connected to node point N
1
while the other end of resistor
16
is connected to ground GND. One end of capacitor
18
is connected to node point N
1
while the other end of capacitor
18
is again connected to ground GND. The input terminal of current source
20
is connected to a voltage source VCC.
FIG. 2A
is a diagram showing an example signal waveform as measured by a conventional peak detector.
FIG. 3A
is a diagram showing the signal waveform shown in
FIG. 2A
after signal attenuation.
For example, when the peak detector
10
shown in
FIG. 1
is used to detect voltage peak, the detected signal before attenuation has a waveform
30
shown in FIG.
2
A. Since the peak detector
10
is incapable of distinguishing between low and high frequencies, output waveform
40
is still quite rugged even after attenuation as shown in FIG.
3
A. In other words, if low frequency signals are not attenuated, signal waveform measured by the peak detector is bound to contain larger ripples.
In addition, several conventional techniques related to the design of peak detectors can be found in the following U.S. Patents.
(1) John D. Young et. al, in “High Speed Gated Peak Detector”, U.S. Pat. No. 4,6620,444.
(2) Robert H. Leonowich et. al, in “Master-Slave Peak Detector”, U.S. Pat. No. 5,254,881.
(3) Stan Dendinger et. al, in “Closed-Loop Peak Detector Topology”, U.S. Pat. No. 5,428,307.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a peak detector. The peak detector comprises of a comparator, an input-trigger device, a gate-width control block, an AND gate, a first current source, a second current source, a first switch, a second switch and a capacitor. The positive terminal of the comparator is used for receiving an input signal. The input terminal of the input-trigger device receives the output signal of the comparator. The input terminal of the gate-width control block is connected to the output terminal of the input-trigger device. One input terminal of the AND gate is connected to the output terminal of the comparator while the other input terminal of the AND gate is connected to one of the output terminals of the gate-width control block. The input terminal of the first current source is connected to a voltage source. The output terminal of the second current source is connected to a ground voltage. The ends of the first switch are connected to the output terminal of the first current source and the negative input terminal of the comparator respectively. Opening or closing of the first switch is controlled by the signal potential at the output terminal of the AND gate. The ends of the second switch are connected to the input terminal of the second current source and the negative terminal input terminal of the comparator respectively. Opening or closing of the second switch is controlled by the signal potential at the other output terminal of the gate-width control block. One end of the capacitor is connected to the negative input terminal of the comparator while the other end of the capacitor is connected to the ground voltage.
The peak detector of this invention uses simple circuits to obtain low frequency energy attenuation. Since the low frequency attenuation can also be programmed, the peak detector is able to find the actual average voltage peak. In addition, since the peak detector has a relatively simple design, the invention can replace the complicated analogue-to-digital converter conventionally used in detecting average energy attenuation after passing through an electric cable. The peak detector can also be used to measure voltage attenuation for signals passing through LAN, transmission medium such as cable or twisted pair or other related products.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4315220 (1982-02-01), Findeisen
patent: 4373140 (1983-02-01), Chin
patent: 4620444 (1986-11-01), Young
patent: 4692692 (1987-09-01), Prelhiere

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