Peak clipping circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307544, H03K 508, H03K 500

Patent

active

051967448

ABSTRACT:
A peak clipping circuit for an integrated circuit of the VLSI type is connected in parallel with the integrated circuit and includes a peak clipping transistor of the bipolar T type and a charge transistor M of the MOS type. The charge transistor has its gate connected to an input of a circuit device of the integrated circuit. The clipping circuit functions to minimize parasitic oscillations at the working level of the input signal.

REFERENCES:
patent: 4661723 (1987-04-01), Masuda et al.
patent: 4786961 (1988-11-01), Avery
patent: 4831343 (1989-05-01), Baron
RCA Technical Note, TN No. 877, Feb. 12, 1971, pp. 1-2; Princeton, NJ. H. F. King, Dynamic Input Clamp For Integrated Circuit Gates.
Patent Abstracts of Japan, vol. 3 No. 135 (E-150) [47] Nov. 10, 1979, JP-A-54 112 156 (Kogyo Gijutsuin) Sep. 1, 1979.

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