Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2003-05-22
2004-06-08
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S459000, C438S476000, C438S479000
Reexamination Certificate
active
06746937
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor integrated circuits and, in particular, to partially-depleted Silicon on Insulator (PD-SOI) substrates and devices.
BACKGROUND OF THE INVENTION
Silicon on Insulator (SOI) technology employs a layer of semiconductor material formed over an insulating layer on a supporting bulk wafer. The structure can be formed by different well-known techniques in the art, for example, separation by implanted oxygen (SIMOX), bonding and etching back (BESOI), and zone melting and recrystallization (ZMR), among others. Typically, the structure comprises a film of monocrystalline silicon formed on a buried layer of silicon oxide which is formed on a monocrystalline silicon substrate. As such, in many SOT applications, an epitaxial (epi) silicon layer is used as a top silicon layer, which is generally formed by one of two methods: (1) bonding followed by etch back; or (2) epitaxial layer transfer (ELTRAN) process.
One technique for the formation of a SOI substrate by a conventional bonding and etching back method of the prior art is illustrated in
FIGS. 1-4
. The process starts with the preparation of a silicon substrate
10
(FIG.
1
). The silicon substrate
10
is thermally oxidized to grow a layer of silicon oxide
12
(FIG.
1
), with a thickness of about 1 micron. Subsequently, an n-type single crystalline silicon substrate
14
is opposed to the silicon oxide layer
12
, as shown in FIG.
2
. The silicon substrate
10
, with the oxide layer
12
, is then contacted with the crystalline silicon substrate
14
, and the resultant structure is heated to a temperature of about 1000° C., so that the n-type crystalline silicon of the crystalline silicon substrate
14
adheres to the silicon oxide layer
12
, as shown in FIG.
3
. Next, as illustrated in
FIG. 4
, the n-type crystalline silicon substrate
14
is polished and its thickness is decreased to approximately 1.5 microns. Thus, a SOI substrate
15
(
FIG. 4
) is formed of the silicon substrate
10
, the silicon oxide layer
12
, and the n-type crystalline silicon substrate
14
.
Field effect transistors such as MOSFETs, which are fabricated in the upper silicon layer of a SOI structure, such as the SOI substrate
15
of
FIG. 4
, have multiple advantages over the transistors fabricated on the conventional bulk silicon substrates. These advantages include, among others, resistance to short-channel effect, increased current drive, higher packing density, and reduced parasitic capacitance. However, despite all these attractive properties, SOI technology still has some drawbacks, which reduce the benefits of using it for high-performance and high-density ultra large scale integrated (ULSI) circuits.
One drawback of the SOI technology is the conductivity of the top Si layer and its inherent floating body effect, which has particular significance for partially-depleted (PD) or non-filly depleted SOI devices. The floating body effect in such devices occurs as a result of the buried oxide that isolates the channel region of such device and allows charge carriers to build up in the channel region. In a partially-depleted MOSFET, charge carriers (holes in an nMOSFET and electrons in a pMOSFET), generated by impact ionization near the drain/source region, accumulate near the source/drain region of the transistor. When sufficient carriers accumulate, they are stored in the floating body, which is formed right below the channel region, and alter the floating body potential. As a result, kinks in the I/V curve occur, the threshold voltage is lowered, and the overall electrical performance of the device may be severely degraded.
To diminish the negative effects of the charge build up, so-called “recombination centers” can be introduced into the transistor channel region. According to this technique, damage areas containing implanted ions are placed where the charges accumulate, so that holes and electrons can combine or recombine and accumulated charges removed.
Another technique for diminishing the negative effects of the charge build up has been to provide an extra electrical connection by adding a contact to the body for hole current collection. However, the currently available hole collection schemes, such as the use of a side-contact, are inefficient, require very complex processing steps, and consume a great amount of device area.
Accordingly, there is a need for an improved method for forming a partially-depleted SOI device having reduced charge build up and accompanying threshold voltage changes and charge leakage. There is also a need for an integrated process for epi-SOI wafer fabrication, in which recombination centers are created with fewer processing steps and which saves wafer area. A defect-free partially-depleted SOI substrate is also needed.
SUMMARY OF THE INVENTION
The present invention provides a simple method for forming a partially-depleted Silicon-on-Insulator (SO) substrate with minimal charge build up to mitigate the floating body effect, which can be further used for the fabrication of SOI devices with reduced threshold voltage and leakage.
The method of the present invention employs a thin Si/Ge epitaxial layer grown between two adjacent epitaxial silicon layers of the partially-depleted SOI substrate. The thin Si/Ge epitaxial layer, grown during the epitaxial growth of silicon, introduces misfit dislocations, which are formed as a result of the lattice mismatch between the silicon and germanium atoms, and which act as both recombination sites and proximity gettering sites. After the growth of the thin Si/Ge epitaxial layer and the formation of the partially-depleted (PD) SOI device, the newly-formed dislocations lie close to the buried oxide and remove the accumulated charges, so that the performance of the partially-depleted (PD) SOI device remains largely unaffected by charge build up.
The above and other advantages and features of the present invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Quach T. N.
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