PCI host bridge multi-priority fairness arbiter

Details PCI host bridge multi-priority fairness arbiter PCI host bridge multi-priority fairness arbiter

1997-05-09

1999-05-18

Ray, Gopal C.

Multiplex communications

Wide area network

Packet switching

395728, 395287, 370462, G06F13/14

Patent

active

059058773

ABSTRACT:
A method and system for allowing one or more attached devices to access a computer bus. The objects of the method and system are achieved as is now described. At some particular instant in time, prioritized queues are loaded with one or more requests for access from one or more devices whose assigned priority levels correspond to the priority of the queue into which the requests for access are loaded. Requests for access, which are resident within a current queue, are preferentially granted in a sequential fashion until the current queue is emptied, after which at least one request for access from a lower in priority queue relative to the current queue is granted before responding to other requests for access, such that at least one request for access is periodically granted from a lower in priority queue relative to the current queue.

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