PCI bus to IEEE 1394 bus translator employing write pipe-lining

Details PCI bus to IEEE 1394 bus translator employing write pipe-lining PCI bus to IEEE 1394 bus translator employing write pipe-lining

1997-04-08

1999-02-23

Auve, Glenn A.

395308, 395850, G06F 1300

Patent

active

058753133

ABSTRACT:
A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.

REFERENCES:
patent: 5751975 (1998-05-01), Gillespie et al.
patent: 5764924 (1998-06-01), Hong
Texas Instruments Publication entitled "TSB12LV21A (PCILynx) IEEE 1394-1995 Bus to PCI Bus Interface," Apr. 1997, pp. 1-17.
Adaptec Technical Reference, "AHA-8940 Functional Specification/PCI-to-1394 Host Adapter," 1996, pp. 2-1 to 2-31.
Publication entitled "Preliminary CXD1947Q, IEEE1394 Link Layer/PCI Bridge LSI," Oct. 1996, pp. 1-4.
1394 HCI PEN Publication entitled "1394 Open Host Controller Interface Specification/Draft 0.93," Apr. 1997, pp. i-xiv, 1-140.

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