Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2000-04-11
2003-07-01
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S182000, C714S042000, C714S726000, C714S715000, C710S100000, C710S110000, C710S313000, C324S537000
Reexamination Certificate
active
06587813
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information handling systems including computer systems and related devices and, more particularly, to a method and apparatus for identifying functional problems in a PCI design via iterative testing of PCI protocol.
BACKGROUND OF THE INVENTION
Once a component of an information handling system has been designed, system designers may need to verify its operation to ensure that it operates as designed and that it interfaces properly with each of the other elements of the system.
In order to verify that each element of a newly designed system functions properly, system verification engineers may create a computer model of the system or components to be tested. Although simulation and design verification software reveal many problems, many designs must undergo lengthy and expensive debug phases before yielding fully operational, full specification parts.
A prior art method of system verification involves the use of exercisers/analyzers. Typically, an exerciser randomly selects operations to be performed or applied to the device under test. The advantage of using exercisers/analyzers is that they tend to provide more complete tests in a shorter time frame. The use of exercisers, however, is not without drawbacks. One problem associated with using random exercisers in a PCI environment is that it is typically a fully automated process with a high level of randomness and thus does not guarantee that a given condition or PCI protocol combination has been tested or that a system has been fully tested. It would, therefore, be desirable to provide an improved PCI verification method and apparatus that can be automated to provide iterative testing of all desired conditions or protocol combinations in a PCI system.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method for the automatic testing of a PCI bus system in an information handling system, such as a computer system, comprising the steps of selecting a PCI command to be tested; programming a PCI master to exhibit predetermined functional behavior during a PCI transaction; asserting the PCI command to initiate a PCI transaction, the transaction comprising transfer of data over the PCI bus; transferring at least a portion of the data; monitoring and recording the behavior of the PCI bus system; determining whether a PCI protocol error has occurred; if an error has occurred, logging the error and halting execution; repeating the process until it is determined that an error has occurred or until the PCI transaction is complete; and, if the PCI transaction is completed, writing data from a first memory location to a second memory location, reading data from the second memory location, and comparing data from the first memory location to data from the second memory location. In a further aspect, one or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values.
In another aspect, the present invention provides a method for the automatic testing of a PCI bus system in an information handling system comprising the steps of initializing a PCI target device, which is programmable to exhibit predetermined functional behavior during a PCI transaction; programming the PCI target device to exhibit the predetermined functional behavior during the PCI transaction; providing a PCI master device, the PCI master device comprising configuration address space, the configuration address space programmable to configure the PCI master device; programming the configuration address space to provide a first set of PCI bus utilization properties for the PCI master device; after the PCI target device is programmed to exhibit the predetermined functional behavior, initiating the PCI transaction, the transaction comprising transfer of data over the PCI bus; transferring at least a portion of the data; monitoring and recording the behavior of the PCI bus system; determining whether a PCI protocol error has occurred; if an error has occurred, logging the error and halting execution; repeating the process until it is determined that an error has occurred or until the PCI transaction is complete; and, if the PCI transaction is complete, writing data from a first memory location to a second memory location, reading data from the second memory location, and comparing data from the first memory location to data from the second memory location. In a further aspect, one or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
REFERENCES:
patent: 5930482 (1999-07-01), Carter et al.
patent: 6324663 (2001-11-01), Chambers
Browen Adam
Grabarek John
Hadley Andrew
Nuffer Stuart
Paulsen Erik
Desta Elias
Hoff Marc S.
LSI Logic Corporation
Suiter-West PC LLO
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