Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-02-11
2001-11-27
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S755090, C324S757020
Reexamination Certificate
active
06323670
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of testing semiconductor circuits, and more specifically to apparatus and methods for failure analysis of packaged integrated circuits.
DESCRIPTION OF THE PRIOR ART
Integrated circuits are commonly packaged in a package configuration referred to as a quad flat package (QFP). In this type of package, the leads are very thin, flat metal conductors. These metal conductors extend outward from the four sidewalls of the flat rectangular package. Inoperative QFP devices are frequently returned to a device analysis department as allegedly defective parts, further testing and failure analysis of the device is to be performed by the device analysis organization. The returned QFP devices are often returned with damaged leads because the device user has performed incoming inspection and in-situ testing. As part of this testing, the devices may have been mounted on a circuit board of a test system. The individual integrated circuit devices may also have been soldered on a circuit board for testing of the device as part of testing the functionality of the entire circuit board.
When an integrated-circuit device is suspected of being defective, the device is removed from the circuit board by desoldering. During this desoldering, the leads of the device may be damaged. This kind of damage to the leads may prevent the integrated circuit device from being tested and may prevent verification that the device was actually defective.
Defective devices must be analyzed and retested to determine the cause of the defect. If the device leads have been damaged, it may be very difficult or even impossible to perform the necessary testing and failure analysis. In addition, other questions about the device cannot be investigated and answered, questions such as how, where, and why the device failed.
Finally, if the leads of the device have been damaged, it is very likely that the most significant aspect of failure analysis cannot be performed, that is, determining the root cause of the failure.
One Prior Art technique for dealing with damaged QFP leads is to manually solder test-lead wires to the damaged (very thin) leads of the QFP. These test-leads establish electrical contact with the leads of the defective device. This soldering operation is difficult to perform with larger packages that may have more than 100 leads. The poor success rate for manually soldering a test-lead wire to a damaged device lead indicates that a better, more efficient technique is needed to allow the retesting of damaged QFP devices.
U.S. Pat. No. 5,481,203 (Appold) shows an adapter for a back failure analysis socket.
U.S. Pat. No. 5,781,021 (Ilani) shows universal fixture-less test equipment.
U.S. Pat. No. 5,674,785 (Farnworth) displays an apparatus for assembling semiconductor package for testing.
U.S. Pat. No. 5,519,332 (Wood et al.) shows a carrier for die testing.
SUMMARY OF THE INVENTION
The principle objective of the present invention is to reduce the time and expense required in preparing or positioning a packaged IC for failure analysis.
Another objective of the present invention is to reduce the number of wire jumpers and switches required to prepare or position a packaged IC for failure analysis.
Another objective of the present invention is to allow for ease of preparing or positioning for failure analysis of IC packages of non-uniform or different sizes.
Another objective of the present invention is to allow backside access to packaged IC's for failure analysis.
Another objective of the present invention is to facilitate the feeding of electrical power and electrical signal stimuli to the packaged IC during failure analysis.
According to the present invention, a Printed Circuit Board (PCB) assembly is provided for mounting an Integrated Circuit (IC) during failure analysis of the IC. The PCB assembly includes a clamping arrangement for holding or clamping the PCB board while test signals and power is supplied to the IC via this clamp. Jumper wires connect the IC to the leads provided on the surface of the PCB, an opening in the PCB allows for backside failure analysis of the IC. The location of this opening is such that access is provided to the back of the IC.
The first embodiment of the present invention provides a Printed Circuit Board assembly onto which a chip or die that is to be analyzed is mounted and that provides for the supply of electrical power and electrical stimuli signals to the chip or die to be analyzed. The chip or die that is to be analyzed is mounted on the printed circuit board with the backside or ball contact side facing upwards, that is facing the printed circuit board. The plastic mould into which the die is mounted is removed down to the level of the die. Electrical jumper wires establish connections between the top of the die and electrical leads mounted on the surface of the PCB.
The second embodiment of the present invention provides a Printed Circuit Board assembly onto which a chip or die that is to be analyzed is mounted and that provides for the supply of electrical power and electrical stimuli signals to the chip or die to be analyzed while at the same time providing for an opening or cut-out within the PCB assembly that is lined up with the chip to be analyzed such that backside analysis on this chip or die can be performed. Under the second embodiment of the present invention the chip or die that is to be analyzed is mounted on the printed circuit board with the backside or ball contact side facing toward the printed circuit board.
REFERENCES:
patent: 3870953 (1975-03-01), Boatman et al.
patent: 4312117 (1982-01-01), Robillard et al.
patent: 4695112 (1987-09-01), Maston et al.
patent: 5481203 (1996-01-01), Appold
patent: 5495179 (1996-02-01), Wood et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5739050 (1998-04-01), Farnworth
patent: 5781021 (1998-07-01), Ilani
patent: 5825171 (1998-10-01), Shin
patent: 5946791 (1999-09-01), Baldwin
patent: 6072323 (2000-06-01), Hembree et al.
Ackerman Stephen B.
Deb Anjan K
Metjahic Safet
Saile George O.
Taiwan Semiconductor Manufacturing Company
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