PBGA electrical noise isolation of signal traces

Details PBGA electrical noise isolation of signal traces PBGA electrical noise isolation of signal traces

2001-07-31

2003-05-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S454000, C438S613000

Reexamination Certificate

active

06566167

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to ball grid array type semiconductor packages, and more particularly to the design of a trace layout to isolate electrical noise between two adjacent sets of signals in a 2-layer PBGA substrate.
BACKGROUND OF THE INVENTION
Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Ball grid array (BGA) packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface substrate. An array of solder balls mounted on the bottom of the substrate are used to attach the package to a PC board or motherboard, as opposed to molded plastic packages that use lead frames on the outer edges of the package substrate to attach the package to the PC board.
A plastic ball grid array (PBGA) is a wire bond package having a 2-layer organic substrate and solder balls.
FIG. 1A
is a cross sectional view showing the layer stack-up of a typical 2-layer BGA substrate. The package
10
includes a substrate
12
, and a die
14
coupled to signal traces
16
on the top surface of the substrate via wire bonds
22
. The substrate
12
typically comprises Bismaleimidie Trizine (BT) or the like. Signal traces
16
on the top layer of the substrate
12
are connected on the bottom of the substrate
12
through vias
18
.
Although 2-layer PBGA substrates
12
offer a low cost packaging solution, 2-layer PBGA substrates
12
suffer from electrical noise between adjacent sets of signals and coupling interference.
In order to minimize the electrical noise and the coupling interference, the normal option is to use a more costly enhanced plastic ball grid array (EPBGA). An EPBGA is a wire bond package that uses
4
-layer organic substrate for better electrical and thermal performance.
A
FIG. 1B
is a cross sectional view showing the layer stack-up of a typical 4-layer substrate. Layer
1
of the substrate
52
is a top signal layer
54
, layer
2
is a ground plane (Vss)
56
, layer
3
is a power plane (Vdd)
58
, and layer
4
is a bottom signal layer
60
. Signal traces are typically patterned on both the top and bottom signal layers
54
and
60
, which are connected to the solder bumps
62
through vias
64
. The thicker substrate
52
and the two extra planes
56
and
58
between the top and bottom layers
54
and
60
help reduce noise. However, a 4-layer EPBGA cost 20-30% more than a 2-layer PBGA of a similar design.
Accordingly, what is needed a method for fabricating a semiconductor package to reduce electrical noise between adjacent signals in a 2-layer PBGA without adding additional layers. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a semiconductor package to reduce electrical noise. The semiconductor package uses a 2-layer substrate that includes an array of solder balls on the bottom. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.
According to the system and method disclosed herein, the present invention effectively isolates noise between adjacent signals without adding additional layers and at low cost.


REFERENCES:
patent: 6133805 (2000-10-01), Jain et al.
Rambus, Direct Rambus ASIC Package Selection Guide Version 0.1, Nov. 1999, pp. 1-18.*
“Direct Rambus ASIC Package Selection Guide Version 0.1,” Rambus Nov. 1999, pp. 1-18.

Affiliated with

Also associated with

Rating

PBGA electrical noise isolation of signal traces does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PBGA electrical noise isolation of signal traces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PBGA electrical noise isolation of signal traces will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3004495