Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1997-10-02
1999-07-13
Utech, Benjamin
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438257, 438262, 438710, H01L 2021
Patent
active
059226196
ABSTRACT:
A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.
REFERENCES:
patent: 4317272 (1981-03-01), Kuo
patent: 4373248 (1983-02-01), McElroy
patent: 4683640 (1987-08-01), Faraone
patent: 4688720 (1987-08-01), Hayashi
patent: 5570314 (1996-10-01), Gill
Deo Duy-Vu
Donaldson Richard L.
Hoel Carlton H.
Holland Robby T.
Texas Instruments Incorporated
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