Etching a substrate: processes – Masking of a substrate using material resistant to an etchant
Reexamination Certificate
2007-12-05
2011-12-27
Alanko, Anita (Department: 1713)
Etching a substrate: processes
Masking of a substrate using material resistant to an etchant
C216S017000, C216S047000, C216S049000, C438S694000, C438S700000, C438S942000, C438S947000, C977S888000, C977S895000
Reexamination Certificate
active
08083958
ABSTRACT:
Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.
REFERENCES:
patent: 6746825 (2004-06-01), Nealey et al.
patent: 7429536 (2008-09-01), Abatchev et al.
patent: 7553760 (2009-06-01), Yang et al.
patent: 7651735 (2010-01-01), Cheng et al.
patent: 7696085 (2010-04-01), Li et al.
patent: 7723009 (2010-05-01), Sandhu et al.
patent: 7892940 (2011-02-01), Edelstein et al.
patent: 2004/0195202 (2004-10-01), Pechenik
patent: 2007/0224823 (2007-09-01), Sandhu
patent: 2008/0103256 (2008-05-01), Kim et al.
patent: 2008/0176767 (2008-07-01), Millward
patent: 2008/0233323 (2008-09-01), Cheng et al.
patent: 2009/0311363 (2009-12-01), Dobisz et al.
Nealey, et al., “Self-Assembling Resists for Nanolithography,” IEEE, 2005, pp. 1-4, Electron Devices Meeting, 2005. IEDM Technical Digest, IEEE Intl., Dec. 2005.
Pending U.S. Appl. No. 11/424,963 “Sub-Lithographic Feature Patterning Using Self-Aligned Self-Assembly Polymers”, filed Jun. 19, 2006, Yang, et al.
Pending U.S. Appl. No. 11/538,550 “Sub-Lithographic Local Interconnects, and Methods for Forming Same”, filed Oct. 4, 2006, Yang, et al.
Pending U.S. Appl. No. 11/552,641 “Sub-Lithographic Gate Length Transistor Using Self-Assembling Polymers”, filed Oct. 25, 2006, Yang, et al.
Pending U.S. Appl. No. 11/627,488 “Sub-Lithographic Interconnect Patterning Using Self-Assembling Polymers”, filed Jan. 26, 2007, Yang, et al.
Li Wai-Kin
Yang Haining S.
Alanko Anita
Cai, Esq. Yuanmin
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
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