Patterning 3D features in a substrate

Details Patterning 3D features in a substrate Patterning 3D features in a substrate

2011-07-26

2011-07-26

Deo, Duy-Vu N (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S707000, C438S725000, C216S058000, C216S083000

Reexamination Certificate

active

07985689

ABSTRACT:
Methods of forming a 3D structure in a substrate are disclosed. A layer of resist is deposited on the substrate. The layer of resist is patterned to define an edge at a predetermined location. The resist is reflowed to form a tapered region extending from the etch. Both the reflowed resist and the substrate are concurrently etched to transfer the tapered profile of the reflowed resist into the underlying substrate to form an angled surface. The etching is discontinued before all of the resist is consumed by the etching.

REFERENCES:
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patent: 6759281 (2004-07-01), Kim et al.
patent: 7439187 (2008-10-01), Ono et al.
patent: 2004/0165637 (2004-08-01), Bullington et al.
patent: 2005/0230348 (2005-10-01), Kido
patent: 2006/0067651 (2006-03-01), Chui

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