Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-03-13
2009-06-23
Graybill, David E (Department: 2894)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000
Reexamination Certificate
active
07550314
ABSTRACT:
A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.
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Arabe Ferdinand Borromeo
Odegard Charles Anthony
Yunus Mohammad
Brady III Wade J.
Graybill David E
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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