Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1996-07-01
1998-06-09
Nguyen, Viet Q.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257773, 364490, 364491, 430311, 430313, 430318, 430312, G03F 726
Patent
active
057639558
ABSTRACT:
A metal layer on an integrated circuit includes active signal lines and fill metal segments. The fill metal segments are polygons. Each fill metal segment at its narrowest has a width which is not greater than 1.25 times a design rule metal pitch for a technology used to fabricate the integrated circuit. In addition, each fill metal segment is separated from every other fill metal segment by spacing which is at least 0.7 times the design rule metal pitch for the technology used to fabricate the integrated circuit. Also, each fill metal segment is separated from every active signal line by spacing which is at least 0.5 times the design rule metal pitch for the technology used to fabricate the integrated circuit.
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M. Ichikawa, et al, Multilevel Interconnect System for 0.35 .mu.m CMOS LSI's with metal dummy planarization process and thin tungsten Wirings, 1995 VMIC Conference, 1995 ISMIC, pp. 254-269.
Findley Paul Raj
Smith Morgan
Nguyen Viet Q.
VLSI Technology Inc.
Weller Douglas L.
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