Pattern verification method, program thereof, and...

Details Pattern verification method, program thereof, and... Pattern verification method, program thereof, and...

2011-07-26

2011-07-26

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Analysis and verification

C716S053000

Reexamination Certificate

active

07987435

ABSTRACT:
A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

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Notice of Reasons for Rejection issued by Japanese Patent Office, mailed on Oct. 19, 2010, in a counterpart Japanese application No. 2005-244448 (4 pages).

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