Pattern synchronizing circuit

Details Pattern synchronizing circuit Pattern synchronizing circuit

1991-06-04

1993-05-11

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

375116, 375119, H04L 708

Patent

active

052107540

ABSTRACT:
An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.

REFERENCES:
patent: 3144515 (1964-08-01), Kaneko
patent: 4802192 (1989-01-01), Eto et al.
patent: 4984238 (1991-01-01), Watanabe et al.
patent: 4984249 (1991-01-01), Long et al.

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