Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-11-15
2002-04-09
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C216S051000, C216S099000, C438S725000, C438S738000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06368982
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to a method for reducing dimensions beyond photolithography limitations during a patterning process by selectively patterning and trimming each of a plurality of layers of different hardmask materials in a successive sequence.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, for fabrication of an integrated circuit structure, a layer of target material
102
is deposited on a semiconductor substrate
104
. For example, for formation of a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the layer of target material
102
may be comprised of polysilicon. For patterning and etching the layer of target material
102
to form the integrated circuit structure, a photoresist structure
106
has been patterned and etched from a layer of photoresist material in a photolithography process as known to one of ordinary skill in the art of integrated circuit fabrication. The photoresist structure
106
has a length
108
and a height
110
.
Referring to
FIGS. 1 and 2
, any exposed region of the layer of target material
102
is etched away to form a target structure
112
of the target material remaining under the photoresist structure
106
. Thus, the target structure
112
has the same length
108
as that of the photoresist structure
106
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
In
FIGS. 1 and 2
, to scale down the length of the target structure
112
, the length
108
of the photoresist structure
106
is scaled down during the photolithography process for forming the photoresist structure
106
. However, photolithography processes for forming the photoresist structure
106
have limitations for a minimum length, as known to one of ordinary skill in the art of integrated circuit fabrication. Nevertheless, dimensions that are smaller than the minimum length achievable with photolithography process limitations are desired as integrated circuit devices are scaled down further.
Referring to
FIGS. 1 and 3
, for achieving such smaller dimensions than achievable with photolithography process limitations, after the photoresist structure
106
is formed to the minimum length possible given photolithography process limitations, the photoresist structure
106
is trimmed to reduce the original length
108
of the photoresist structure
106
by a trim length
114
using a photoresist trimming process as known to one of ordinary skill in the art of integrated circuit fabrication. During such a photoresist trimming process, the dimensions of the photoresist structure
106
are reduced by the trim length
114
at the two sides and at the top of the photoresist structure
106
as illustrated in FIG.
3
. In this manner, the target structure formed from etching away any exposed region of layer of the target material
102
has the scaled down length of the photoresist structure
106
of FIG.
3
.
During the photoresist trimming process, the two sides and the top of the photoresist structure
106
are trimmed by the substantially same trim length
114
. Thus, with the photoresist trimming process of the prior art, the minimum length of the photoresist structure
106
is limited by the height
110
of the photoresist layer forming the original photoresist structure
106
.
Furthermore, referring to
FIG. 4
, even if the photoresist structure
106
having a small length were formed with a relatively thick photoresist layer, the aspect ratio (defined as the height to the length) of the photoresist structure
106
is high. Because photoresist material is a malleable material as known to one of ordinary skill in the art of integrated circuit fabrication, the photoresist structure
106
having high aspect ratio is likely to deform in shape by bending over.
Referring to
FIG. 5
, a hardmask structure
116
having a length
118
and comprised of a hardmask material (such as silicon nitride for example) that is not as malleable as photoresist material may be formed to pattern the layer of target material
102
. The dimensions of the hardmask structure
116
may be further scaled down in a hardmask trimming process as known to one of ordinary skill in the art of integrated circuit fabrication. However, because the dimensions of the hardmask structure
116
would be trimmed at both the side surfaces and the top surface of the hardmask structure
116
during the hardmask trimming process, the minimum length of the hardmask structure
116
is limited by the original height of the hardmask structure
116
, similar to the photoresist structure
106
.
Furthermore, referring to
FIG. 5
, when the hardmask structure
116
is comprised of a dielectric material (such as silicon nitride for example), having a large height for a large trim length, the top corners of the hardmask structure
116
become rounded during the hardmask trimming process to form the hardmask structure
116
, as known to one of ordinary skill in the art of integrated circuit fabrication. With such rounded top corners of the hardmask structure
116
, the thickness of the hardmask structure
116
tapers to be smaller at the sides of the hardmask structure
116
down toward the layer of target material
102
. Referring to
FIGS. 5 and 6
, during etching of the target material
102
to form the target structure
112
, the portion of the hardmask structure
116
having the smaller thickness at the sides of the hardmask structure
116
down toward the layer of target material
102
may etch away to result in an undesired smaller length
120
of the hardmask structure
116
and the target structure
112
. Thus, the length of the target structure
112
is more difficult to predict and control when using the single hardmask structure
116
.
Despite such disadvantages of trimming the single photoresist structure
106
of the prior art (as illustrated in
FIGS. 1
,
2
,
3
, and
4
) or the single hardmask structure
116
of the prior art (as illustrated in FIGS.
5
and
6
), the dimensions of the target structure are desired to be further scaled down.
Thus, a mechanism is desired for scaling down the dimensions of the target structure beyond photolithography process limitations without the disadvantages of trimming the single photoresist structure
106
of the prior art or the single hardmask structure
116
of the prior art.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a plurality of layers of different hardmask materials having relatively small thickness are selectively patterned and trimmed in a successive sequence to achieve dimensions beyond photolithography process limitations.
In one embodiment of the present invention, in a method for patterning a layer of target material on a semiconductor substrate, the method includes a step of depositing a layer of first hardmask material on the layer of target material. The first hardmask material is different from the target material. A layer of second hardmask material is deposited on the layer of first hardmask material, and the second hardmask material is different from the first hardmask material. A layer of patterning material is deposited on the layer of second hardmask material. The layer of patterning material is patterned and etched such that a patterned structure of the patterning material remains on the second layer of second hardmask material.
Any exposed region of the layer of second hardmask material is etched using a first etching reactant such that a second hardmask structure is formed from the second hardmask material remaining under the patterned structure and on the layer of first hardmask material. The first etchi
Advanced Micro Devices , Inc.
Choi Monica H.
Powell William A.
LandOfFree
Pattern reduction by trimming a plurality of layers of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern reduction by trimming a plurality of layers of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern reduction by trimming a plurality of layers of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2881136