Pattern-producing method for semiconductor device

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification

Reexamination Certificate

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C430S030000

Reexamination Certificate

active

07966584

ABSTRACT:
Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

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Notice of Reasons for Rejection mailed Mar. 25, 2008, issued by the Japanese Patent Office for Application No. 2003-420984, and English translation thereof.
Notification for Filing Opinion mailed Apr. 17, 2006, issued by the Korean Intellectual Property Office in counterpart Korean Application No. 10-2004-106850 and English translation thereof.

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