Computer graphics processing and selective visual display system – Display driving control circuitry – Intensity or color driving control
Reexamination Certificate
2001-08-02
2003-10-07
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Intensity or color driving control
C345S691000, C345S099000, C345S087000
Reexamination Certificate
active
06630940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern output circuit for and a pattern output method of generating a pattern output corresponding to data, by switching an ON/OFF ratio by timesharing in accordance with the data and pattern information corresponding to the data.
2. Description of the Related Art
For example, in an LCD (Liquid Crystal Display) driver, display of a sub-pixel located at an intersection of a row specified by a common driver and a column specified by a segment driver is controlled. A gray scale display is implemented by controlling timesharing, a specific ratio (pattern) for an individual sub-pixel that turns ON/OFF within a certain period of time. In a display device of a matrix mode such as an LCD and the like, a pattern output circuit is used for generating a pattern output signal that controls the gray scale display of the individual sub-pixel.
FIG. 5
is a schematic block diagram showing one example of a conventional pattern output circuit.
This pattern output circuit
52
is used in a segment driver of the LCD described above, and is formed with an address register
12
, a memory
14
b
, a decoder
16
, a pattern selection circuit
18
and a register
20
b
. Further, the same figure schematically shows a circuit that utilizes a pattern output signal from the pattern output circuit
52
as a rear stage circuit
24
.
In the following, with reference to a timing chart shown in
FIG. 6
, the operation of the pattern output circuit
52
will be described.
As shown in the timing chart of
FIG. 6
, at first, an address signal is held in the address register
12
in synchronization with a falling edge of a clock signal CLK. The address signal held in the address register
12
is input into the memory
14
b
, and the gray scale data stored in a memory address corresponding to the address signal is output from the memory
14
b
. The decoder
16
decodes the gradation data output from the memory
14
b.
A decoded signal output from the decoder
16
is input into the pattern selection circuit
18
along with a pattern information signal. The pattern information signal is time-series information for controlling a ratio of which the individual sub-pixel is turned ON/OFF, corresponding to each gray scale, is input into the pattern selection circuit
18
in synchronization with the falling edge of the clock signal CLK. A pattern selection output signal corresponding to the gray scale data is output from the pattern selection circuit
18
, in accordance with the decoded signal and the pattern information signal.
The pattern selection output signal is held in the register
20
b
in synchronization with the falling edge of the clock signal CLK, and then output from the register
20
b
as a pattern output signal. Accordingly, the pattern output signal is delayed by one clock time-interval with respect to the pattern selection output signal, as shown in the timing chart of FIG.
6
. Thereafter, the pattern output signal output from the register
20
b
is input into the rear stage circuit
24
, and is utilized in synchronization with the clock signal CLK in the rear stage circuit
24
.
As described above, in the conventional pattern output circuit
52
, the pattern output signal is delayed by one clock time-interval with respect to the pattern selection output signal. Consequently, it cannot be used in an application which has a time limit less than the period from an input to an output and must utilize the period of the initial clock-time interval of which one cycle (Tcycle). Further, because the size of the register
20
b
is large, there is a problem with the chip size being significantly affected in an application having a large number of pattern selection output signals, such as the LCD driver, for example.
SUMMARY OF THE INVENTION
Accordingly, to solve the problems in the conventional art described above, it is an object of the present invention to provide a pattern output circuit and a pattern output method which is capable of obtaining a pattern output signal with a minimal delay time, and which is capable of significantly reducing the size of a circuit.
In order to achieve the above-mentioned objects, the present invention provides a pattern output circuit that includes a pattern selection circuit for outputting a pattern selection output signal in response to a pattern information signal to control an ON/OFF ratio by timesharing, and a temporary holding circuit for holding the pattern selection output signal and for outputting it as a pattern output signal. The temporary holding circuit holds the pattern selection output signal in synchronization with a holding signal that is the difference between a clock signal and a delayed clock signal. The delayed clock signal in this case is a delayed signal of the clock signal.
Preferably, the pattern output circuit further includes a memory for storing data, and a decoder for decoding data output from the memory and for outputting a decoded signal. The pattern selection circuit outputs the pattern selection output signal in accordance with the decoded signal and the pattern information signal.
Additionally, the pattern output circuit further includes a delayed clock signal generating circuit for generating the delayed clock signal, and a holding signal creating unit for creating the holding signal.
Still further, the delayed clock signal generating circuit includes a dummy cell having the same structure as a memory cell in the memory, and the dummy cell is provided at the furthest location away from a clock signal input terminal of the memory.
The object of the present invention can be also achieved by a pattern output circuit that includes a memory for storing data, a decoder for decoding data output from the memory and for outputting a decoded signal therefrom, a pattern selection circuit for outputting a pattern selection output signal in response to the decoded signal and a pattern information signal to control an ON/OFF ratio by timesharing, a temporary holding circuit for holding the pattern selection output signal and for outputting it as a pattern output signal, and a delayed clock signal generating circuit for generating a delayed clock signal that is a delayed signal of a clock signal. The temporary holding circuit holds the pattern selection output signal in synchronization with a holding signal that is the difference between the clock signal and the delayed clock signal.
It is preferable that in the pattern output circuit of the present invention, the temporary holding circuit includes a first transfer-gate, the pattern selection output signal being input into one of the terminals thereof, a first inverter for outputting the pattern output signal, an input thereof is connected to the other terminal of the first transfer-gate, a second inverter into which the pattern output signal is input, a second transfer-gate, an output of the second inverter is input into one of the terminals thereof, and the other terminal thereof is connected to both the other terminal of the first transfer-gate and the input of the first inverter. The first and second transfer-gates are configured so that the ON/OFF ratio thereof is controlled exclusively by the holding signal.
Preferably, in the pattern output circuit of the present invention, the temporary holding circuit further includes a pull-up transistor that the pattern output signal is input to a gate thereof, for pulling up the other terminal of the first transfer-gate and the input of the first inverter.
Additionally, in the pattern output circuit of the present invention, the temporary holding circuit includes a first transfer-gate, the pattern selection output signal being input into one of the terminals thereof, a first inverter for outputting the pattern output signal, an input thereof is connected to the other terminal of the first transfer-gate, a second inverter into which the pattern output signal is input, a second transfer-gate, an output of the second inverter is input into one of the terminals thereof, and the oth
Chang Kent
Kawasaki Steel Corporation
Sheng Tom
LandOfFree
Pattern output circuit and pattern output method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern output circuit and pattern output method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern output circuit and pattern output method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3142697