Pattern matching apparatus

Details Pattern matching apparatus Pattern matching apparatus

1997-09-17

2001-02-27

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S343000

Reexamination Certificate

active

06195402

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates a pattern matching apparatus of a communication apparatus with employment of a multi-value modulation method. More specifically, the present invention is directed to such a pattern matching apparatus that even when a length of a pattern is extended, a total number of adders as well as a total number of D-FFs (D type flip-flops) are not increased.
Referring now to drawings, the conventional pattern matching apparatus will be described.
FIG. 9
is a schematic block diagram for representing an arrangement of one conventional pattern matching apparatus.
FIG. 10
illustrates a frame format used to explain operation of the conventional pattern matching apparatus depicted in FIG.
9
.
As represented in
FIG. 10
, in the conventional pattern matching apparatus, the known symbol pattern (normally, called as a “synchronization word” or a “unique word”, and will be referred to as a “UW pattern (unique word pattern) hereinafter)” is detected from the received signal, and this known symbol pattern is utilized as follows:
To synchronize a frame/slot,
To detect a head symbol of the reception signal,
To judge reliability of the received signal etc.
Next, operations of the conventional pattern matching apparatus shown in
FIG. 9
will now be explained with reference to FIG.
11
. In
FIG. 11
, symbol x(kT) indicates the received signal.
At a Time Instant 0T
An input signal x(0T) is multiplied by coefficients a
0
, a
1
, a
2
, a
3
, and a
4
. Since an initial value of D-FF
623
is equal to 0, an output y(0T) is given by y(0T)=a
4
*x(0T). At this time, since the quantity of input data is not equal to that of the patterns, no UW pattern detection decision is carried out.
At a Time Instant 1T
Since an initial value of a D-FF located at one preceding stage is equal to 0, the multiplication results between the input signal x(0T) and the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
are stored into the D-FF respectively. Another input signal x(1T) is multiplied by the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
. Since the value of the D-FF
623
is equal to a
3
*x(0T), an output y(1T) is given by y(1T)=a
3
*x(0T)+a
4
*x(1T). At this time, since the quantity of the input data is not equal to that of the patterns, no UW pattern detection decision is carried out.
At a Time Instant 2T
The result of the (multiplication result) between an input signal x(1T) and the coefficient a
0
is stored into a D-FF
605
. An result of the (addition result) obtained by adding the 1-T preceding value of the DD-FF
605
to the multiplication result between the input signal x(1T) and the coefficient a
1
is stored into a D-FF
611
. Another addition result obtained by adding the 1-T preceding value of the D-FF
611
to the multiplication result between the input signal x(1T) and the coefficient a
2
is stored into a D-FF
617
. Another addition result obtained by adding the 1-T preceding value of the D-FF
617
to the multiplication result between the input signal x(1T) and the coefficient a
3
is stored into a D-FF
623
. Another input signal x(2T) is multiplied by the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
. Since the value of the D-FF
623
is equal to:
a
2
*x
(0
T
)+
a
3
*x
(1
T
),
an output y(2T) is given by:
y
(2
T
)=
a
2
*x
(0
T
)+
a
3
*x
(1
T
)+
a
4
*x
(2
T
).
At this time, since the quantity of the input data is not equal to that of the patterns, no UW pattern detection decision is carried out.
At a Time Instant 3T
The multiplication result between the input signal x(2T) and the coefficient a
0
is stored into the D-FF
605
. An addition result obtained by adding the 1-T preceding value of the D-FF
605
to the multiplication result between the input signal x(2T) and the coefficient a
1
is stored into the D-FF
611
. Another addition result obtained by adding the 1-T preceding value of the D-FF
611
to the multiplication result between the input signal x(2T) and the coefficient a
2
is stored into the D-FF
617
. Another addition result obtained by adding the 1-T preceding value of the D-FF
617
to the multiplication result between the input signal x(2T) and the coefficient a
3
is stored into the D-FF
623
. Another input signal x(3T) is multiplied by the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
. Since the value of the D-FF
623
is equal to:
a
1
*x
(0
T
)+
a
2
*x
(1
T
)+
a
3*
x
(2
T
),
an output y(3T) is given by:
y
(3
T
)=
a
1
*x
(0
T
)+
a
2
*x
(1
T
)+
a
3
*x
(2
T
)+
a
4
*x
(3
T
).
At this time, since the quantity of the input data is not equal to that of the patterns, no UW pattern detection decision is carried out.
At a Time Instant 4T
The multiplication result between an input signal x(3T) and the coefficient a
0
is stored into the D-FF
605
. An addition result obtained by adding the 1-T preceding value of the D-FF
605
to the multiplication result between the input signal x(3T) and the coefficient a
1
is stored into the D-FF
611
. Another addition result obtained by adding the 1-T preceding value of the D-FF
611
to the multiplication result between the input signal x(3T) and the coefficient a
2
is stored into the D-FF
617
. Another addition result obtained by adding the 1-T preceding value of the D-FF
617
to the multiplication result between the input signal x(3T) and the coefficient a
3
is stored into the D-FF
623
. Another input signal x(4T) is multiplied by the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
. Since the value of the D-FF
623
is equal to:
a
0
*x
(0
T
)+
a
1
*x
(1
T
)+
a
2
*x
(2
T
)+
a
3
*x
(3
T
),
and output y(4T) is given by:
y
(4
T
)=
a
0
×x
(0
T
)+
a
1
×x
(1
T
)+
a
2
×x
(2
T
)×(2
T
)+
a
3
*x
(3
T
)+
a
4
*x
(4
T
).
At this time, since the quantity of the input data is equal to that of the pattern, the UW pattern detection decision is commenced.
The UW pattern may be detected/judged by repeatedly performing the above-explained calculation process based upon a value y(kT) by comparing this value y(kT) with the threshold value. This value y(kT) is calculated by the following formula (1):
y
(
kT
)=
a
0
*x
((
k−
4)
T
)+
a
1
*x
((
k−
3)
T
)+
a
2
*x
((
k−
2)
T
)+
a
3
*x
((
k−
1)
T
)+
a
4
*x
(
kT
)  (1)
It should be noted that when the input signal x(kT) corresponds to digital data after the decoding operation, as represented in
FIG. 12
, the detection/judgement of the UW pattern may be realized not by way of the multiplications by the coefficients a
0
, a
1
, a
2
, a
3
, and a
4
, buy by way of an exclusive OR gating operation.
SUMMARY OF THE INVENTION
As previously described, since the conventional pattern matching apparatus is arranged by the multipliers, the adders, and the D-FFs, when the length of the pattern increases, the total number of these adders and the bit number of the adder increases. This causes the circuit scale to increase. Also, in such a multi-value modulation system where a plurality of bits is represented by 1 symbol, the total number of the adders is increased. This increase is shown in FIG.
13
. That is,
FIG. 13
exemplifies a 2-value modulation system where 2 bits are represented by 1 symbol.
The present invention solves the above-described problems, and therefore, has an object to provide a pattern matching apparatus capable of reducing the total number of adders and D-FFs even when a length of a pattern increases.
A pattern matching apparatus of the present invention is realized by utilizing the feature of the multi-value modulation system such as M bits/1 symbol. That is, a coincident bit number between the received 1 symbol (M bits) and 1 symbol (M bits) of the known pattern is detected, and this detected bit number is added to each other, so that when a length of a UW pattern is N bits, the total number of adders can be reduced to N/M.
A pattern matching apparatus is described comprising: in the case of a multi-value modulation system where a plurality of bits is re

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