Pattern management method and pattern management program

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification

Reexamination Certificate

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Details

C716S050000, C716S052000, C716S053000, C716S054000, C716S055000, C430S005000, C430S030000

Reexamination Certificate

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08086973

ABSTRACT:
A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.

REFERENCES:
patent: 5627625 (1997-05-01), Ogawa
patent: 6727028 (2004-04-01), Kotani et al.
patent: 6952818 (2005-10-01), Ikeuchi
patent: 7252910 (2007-08-01), Hasegawa et al.
patent: 7601471 (2009-10-01), Osawa et al.
patent: 2000-260706 (2000-09-01), None
patent: 2004-184633 (2004-07-01), None

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