Pattern layout of CMOS image sensor

Details Pattern layout of CMOS image sensor Pattern layout of CMOS image sensor

2006-04-13

2008-09-30

Luu, Thanh X. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C348S302000, C348S308000

Reexamination Certificate

active

07429722

ABSTRACT:
A solid-state image pickup device comprises pixels and output circuits. The pixels are arranged two-dimensionally with a vertical and a horizontal, with pixels vertically adjacent to each other forming a pair. The output circuits are provided so as to extend from the spacing part of a pair of pixels vertically adjacent to each other to the spacing part of a pair of pixels horizontally adjacent to the pair of pixels. The output circuits output information corresponding to the signal charge read from a selected one of the pair of pixels. A unit cell is composed of a pair of pixels vertically adjacent to each other and an output circuit corresponding to the pair of pixels. Such unit cells are arranged in a checkered pattern. One of the pair of pixels in a unit cell diagonally adjacent to the pair of pixels is arranged in the same horizontal line.

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Keiji Mabuchi, et al., “CMOS Image Sensors Comprised of Floating Diffusion Driving Pixels With Buried Photodiode”, IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004, pp. 2408-2416.

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