Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2000-03-14
2003-08-05
Chen, Wenpeng (Department: 2624)
Image analysis
Applications
Manufacturing or product inspection
C430S311000
Reexamination Certificate
active
06603875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to pattern inspection methods, and pattern inspection apparatuses, and recording media which store pattern inspection programs. More particularly, the present invention relates to a pattern inspection method and a pattern inspection apparatus for pattern inspection by the use of an electro-optical system, and a recording medium which records a pattern inspection program.
As pattern designs on printed wiring boards or photomasks have been rapidly improved by programs such as a CAD (Computer Aided Design) program, pattern inspection has been becoming more and more important, because of the increasing difficulties in guaranteeing high quality and high performance. There are two types of pattern inspection methods: one is a continuity inspection type, and the other is a visual inspection type.
As a conventional pattern inspection method of the visual inspection type, there is a die-to-die inspection technique for carrying out pattern inspection by comparing two neighboring chips (dies). Also, there is a die-to-database inspection technique for carrying out pattern inspection by comparing a chip with design data.
2. Description of the Related Art
FIG. 1
is a block diagram of a die-to-die pattern inspection apparatus and a die-to-database pattern inspection apparatus.
FIG. 2
is a flowchart of operations of the apparatuses shown in FIG.
1
.
The apparatus comprises two optical detectors (objectives)
4
a
and
4
b.
The optical detector
4
a
and a light receiving member
6
a
capture the image data of a chip
3
a
(step S
16
), and the optical detector
4
b
and a light receiving member
6
b
capture the image data of a chip
3
b
to be inspected (step S
22
). The captured data of the chip
3
a
is stored in an image memory
7
a
(step S
20
), while the captured image data of the chip
3
b
is stored in an image memory
7
b
(step S
24
). Here, the optical detectors
4
a
and
4
b
are situated in such positions that they can simultaneously scan the image data at the same locations on the chips
3
a
and
3
b.
The above process is the image data capturing process in the die-to-die pattern inspection. In the case of the die-to-database pattern inspection, on the other hand, a data conversion unit
14
converts design data
16
into image data (step S
30
), and the converted data, instead of the image data captured by the optical detector
4
a
and the light receiving member
6
a,
is stored in the image memory
7
a
(step S
20
).
In both cases of the die-to-die pattern inspection and the die-to-database pattern inspection, a pattern compound circuit
8
compares the image data stored in the image memory
7
a
with the image data stored in the image memory
7
b
(step S
36
), and supplies the comparison result to a defect detecting circuit
9
. In accordance with the comparison result, the defect detecting circuit
9
detects defects (step S
38
).
Although the apparatuses shown in
FIG. 1
have the two optical detectors
4
a
and
4
b,
it is also possible to employ only one optical detector in the die-to-die pattern inspection.
FIG. 3
is a block diagram of another die-to-die pattern inspection apparatus.
FIG. 4
is a flowchart of the apparatus of FIG.
3
. In these figures, the same components as in
FIGS. 1 and 2
are denoted by the same reference numerals.
The apparatus of
FIG. 3
has an optical detector (an objective)
4
. The optical detector
4
and a light receiving member
6
capture the image data of the chip
3
a
(step S
56
). A switch
17
is then connected to the image memory
7
a
so as to store the image data of the chip
3
a
in the image memory
7
a
(step S
58
). The optical detector
4
and a light receiving member
6
capture the image data of the other chip
3
b
(step S
56
). This time, the switch
17
is connected to the image memory
7
b
so as to store the image data of the chip
3
B in the image memory
7
b
(step S
60
).
The pattern compound circuit
8
then compares the image data stored in the image memory
7
a
with the image data stored in the image memory
7
b
(step S
62
), and supplies the comparison result to the defect detecting circuit
9
. In accordance with the comparison result, the defect detecting circuit
9
detects defects (step S
64
).
Each of the defects detected as shown in the flowcharts of
FIGS. 2 and 4
is checked by visual inspection.
FIG. 5
is a flowchart of the defect evaluation procedure.
After the defect detection is completed, the detected defects are read out of a defect information memory
10
one by one (step S
84
), and the read-out information is processed so that the position of each defect can be visually seen (step S
86
). For instance, the defective point is enlarged and displayed.
A user evaluates the defects one by one, and determines whether the defect is a false defect that is allowable (step S
88
). The false defects are not pattern disconnection or short circuits, but are differences between the design data and each chip. For instance, the round corners of patterns formed on a chip represent such differences.
If the defect is determined to be a false defect, the defect information corresponding to the defect is rewritten (step S
90
). This process is carried out for every detected defect, so that false defects are eliminated from the final defect data set.
In the die-to-die pattern inspection using the apparatus shown in
FIG. 1
, however, the two optical detectors
4
a
and
4
b
complicate the structure, resulting in high production costs. The die-to-die pattern inspection using the apparatus shown in
FIG. 3
also has a problem that a large-capacity image memory is required, which also results in high production costs.
In the die-to-database pattern inspection, it is necessary to prepare the design data and convert the design data into image data for inspection. This data conversion takes a very long time and results in poor operation efficiency.
In any of the above inspections, pattern images should be accurately compared, and therefore a high-precision apparatus is required.
Furthermore, patterns formed on a chip normally have round corners, and cannot be compared with the image data converted from the design data. To perform proper comparisons, the round corners need to be adjusted for. However, it is difficult to process adjustments for the round corners, because such a process often leads to wrong detection and many false defects. To avoid the wrong detection, the defect evaluation procedure shown in
FIG. 5
is needed in order to evaluate defect information containing false defect information so as to eliminate the false defects from the final defect data set. However, the defect evaluation procedure takes a very long time, and the visual evaluation often reduces inspection reliability.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide pattern inspection methods, pattern inspection apparatuses, and recording media which store pattern inspection programs, in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a pattern inspection method and a pattern inspection apparatus, by which pattern inspection is carried out with a simpler mechanical configuration following a simpler procedure. Another specific object of the present invention is to provide a recording medium which records a pattern inspection program for carrying out pattern inspection by the above pattern inspection method or the above pattern inspection apparatus.
The above objects of the present invention are achieved by a pattern inspection method which comprises the steps of:
generating first image data from a pattern image captured from a sample;
obtaining a first pattern number which is the number of patterns contained in the first image data;
generating second image data by reducing the four sides of each pattern contained in the first image data by a predetermined width;
obtaining a second pattern number which is the number of patterns contained in the
Kobayashi Ituo
Matsuyama Takayoshi
LandOfFree
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