Pattern generator for cycle delay

Details Pattern generator for cycle delay Pattern generator for cycle delay

1995-08-15

1997-10-28

Beausoliel, Jr., Robert W.

Excavating

371 62, 395552, G01R 3128

Patent

active

056823932

ABSTRACT:
A pattern generator facilitates the pattern generation of an electronics device to be measured such as SDRAM where each input and output signal cycle is not matched. The pattern generator includes a first address signal delay section that applies a cycle delay to a first address signal based on the number set in a first delay register, a second address signal delay section that applies a cycle delay to a second address signal based on the number set in a second delay register, a data signal delay section that applies a cycle delay to a data signal based on the number set in a data delay register, a control signal delay section that applies cycle delay to a control signal based on the number set in a control delay register.

REFERENCES:
patent: 4415984 (1983-11-01), Gryger et al.
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 5062109 (1991-10-01), Ohshima et al.
patent: 5265102 (1993-11-01), Saito
patent: 5321700 (1994-06-01), Brawn et al.
patent: 5390192 (1995-02-01), Fujieda
patent: 5426771 (1995-06-01), Asprey et al.

Affiliated with

Also associated with

Rating

Pattern generator for cycle delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pattern generator for cycle delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern generator for cycle delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1030561