Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-04-09
2000-05-23
Follansbee, John A.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 13, 712 14, 712 15, 712 16, 712 20, 712 22, G06F 1500
Patent
active
060676094
ABSTRACT:
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming "supercells" within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.
REFERENCES:
patent: 3287703 (1966-11-01), Slotnick
patent: 3643236 (1972-02-01), Kolankowsky et al.
patent: 3815095 (1974-06-01), Wester
patent: 4167780 (1979-09-01), Hayashi
patent: 4187551 (1980-02-01), Nutter et al.
patent: 4215401 (1980-07-01), Holsztynski et al.
patent: 4309755 (1982-01-01), Lanty
patent: 4314349 (1982-02-01), Batcher
patent: 4380046 (1983-04-01), Fung
patent: 4384273 (1983-05-01), Ackland et al.
patent: 4489381 (1984-12-01), Lavallee et al.
patent: 4507726 (1985-03-01), Grinberg et al.
patent: 4511967 (1985-04-01), Witalka et al.
patent: 4517659 (1985-05-01), Chamberlain
patent: 4524455 (1985-06-01), Holsztynski et al.
patent: 4533993 (1985-08-01), McCanny et al.
patent: 4541115 (1985-09-01), Werth
patent: 4546428 (1985-10-01), Morton
patent: 4573116 (1986-02-01), Ong et al.
patent: 4574394 (1986-03-01), Holsztynski et al.
patent: 4628481 (1986-12-01), Reddaway
patent: 4635292 (1987-01-01), Mori et al.
patent: 4660155 (1987-04-01), Thaden et al.
patent: 4667308 (1987-05-01), Hayes et al.
patent: 4720780 (1988-01-01), Dolecek
patent: 4739474 (1988-04-01), Holsztynski
patent: 4739476 (1988-04-01), Fiduccia
patent: 4752893 (1988-06-01), Guttag et al.
patent: 4769779 (1988-09-01), Chang et al.
patent: 4884190 (1989-11-01), Ngai et al.
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5095527 (1992-03-01), Uramoto et al.
patent: 5179714 (1993-01-01), Graybill
patent: 5276819 (1994-01-01), Rau et al.
patent: 5379444 (1995-01-01), Mumme
patent: 5421019 (1995-05-01), Holsztynski et al.
patent: 5606707 (1997-02-01), Tomassi et al.
patent: 5805915 (1998-09-01), Wilkinson et al.
patent: 5822608 (1998-10-01), Dieffenderfer et al.
Myung Hoon Sunwoo, et al., "A Sliding Memory Plane Array Processor," IEEE Transactions on Parallel and Distributed Systems, vol. 4, No. 6, Jun. 193, pp. 601-612.
John T. Burkley, MPP VLSI Multiprocessor Integrated Circuit Design, published in The Massively Parallel Processor, pp. 206-216, ed. J.L. Potter, (MIT Press, 1985).
W.F. Wong & K.T. Lua, "A preliminary evaluation of a massively parallel processor: GAPP," Microprocessing and Microprogramming, pp. 53-62, vol. 29, No. 1, Jul. 1990, Amsterdam, NL.
Alcolea et al., "FAMA Architecture: Implementation details," Proceedings of IECON '87: 1987 International Conference on Industrial Electronics, Control, and Instrumentation, pp. 737-744, vol. 2, No. 3-6, 1987, Cambridge, Massachusetts.
A. Boubekeur et al., "A Real Experience on Configuring a Wafer Scale 2-D Array of Monobit Processors," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, pp. 637-644, vol. 16, No. 7, Nov. 1993, New York, U.S.
Donald W. Blevins, et al., "Processing Element and Custom Chip Architecture for the BLITZEN Massively Parallel Processor," Technical Report TR87-22, pp. 1-27, published Oct. 22, 1987, by The Microelectronics Center of North Carolina.
R. Michael Hord, "Parallel Supercomputing in SIMD Architectures," pp. 85-90; 143-149; 205-217; 312-324; and 356-359, published 1990 by CRC Press.
Charles C. Weems et al., "The Image Understanding Architecture," pp. 21-27, COINS Technical Report 87-76.
John Smit, "Architecture Descriptions for the Massively Parallel Processor (MPP) and the Airborne Associative Processor (ASPRO)," published Aug. 8, 1980 by Goodyear Aerospace Corporation GER-16785.
"An Evaluation of Some Chips for Image Processing," by T. J. Fountain for University College London, Department of Physics and Astronomy.
"Geometric Arithmetic Parallel Processor", NCR publicaiton, Model No. NCR45CG72.
J. R. Rochez, "Calculateur Cellulaire Universel Destine a L'Etude Des Structures Cellularies Specialisees," Digital Processes, vol. 3, No. 2, pp. 121-138 (1977).
P. Franzon, "Interconnect Strategies for Fault Tolerant 2D VLSI Arrays," IEEE International Conference on Computer Design: VLSI in Computers pp. 230-233, Oct. 1986.
Timothy Bridges, "The GPA Machine: A Generally Partitionable MSIMD Architecture", IEEE, pp. 196-203, Feb. 1990.
Abercrombie Andrew P.
Meeker Woodrow L.
Follansbee John A.
Nguyen Dzung C.
TeraNex Inc.
LandOfFree
Pattern generation and shift plane operations for a mesh connect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern generation and shift plane operations for a mesh connect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern generation and shift plane operations for a mesh connect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1844534