Pattern forming method and system, and method of...

Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle

Reexamination Certificate

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Details

C716S051000, C716S052000, C716S053000, C716S054000, C430S005000, C430S030000

Reexamination Certificate

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08042067

ABSTRACT:
A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.

REFERENCES:
patent: 6316163 (2001-11-01), Magoshi et al.
patent: 6399260 (2002-06-01), Kikuchi
patent: 6570174 (2003-05-01), Tounai et al.
patent: 6853743 (2005-02-01), Kotani et al.
patent: 2002/0043615 (2002-04-01), Tounai et al.
patent: 2003/0223630 (2003-12-01), Adel et al.
patent: 2005/0034093 (2005-02-01), Yamauchi
patent: 09-319067 (1997-12-01), None
patent: 10-055059 (1998-02-01), None
patent: 2000-258892 (2000-09-01), None
patent: 2001-083689 (2001-03-01), None
patent: 2002-131882 (2002-05-01), None
Notification of Reasons for Rejection from the Japanese Patent Office, mailed Oct. 2, 2007.

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