Photocopying – Projection printing and copying cameras – Step and repeat
Reexamination Certificate
2000-06-29
2003-02-04
Nguyen, Henry Hung (Department: 2851)
Photocopying
Projection printing and copying cameras
Step and repeat
C355S055000, C355S077000
Reexamination Certificate
active
06515733
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-187029, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a pattern exposure apparatus and method for use in transferring a circuit pattern of a mask to a semiconductor wafer in manufacturing a semiconductor device, and more particularly, an apparatus and method for controlling the surface of the semiconductor wafer on which light is applied, by tilting the semiconductor wafer.
When a semiconductor element is formed on a semiconductor wafer by a conventional method, a so-called light-exposure step is usually employed. In the light exposure step, a circuit pattern drawn on a reticle is projected onto the wafer by a light exposure apparatus called a stepper and thereby reduced and transferred onto the wafer.
In the light exposure step, the circuit pattern of a single chip or a plurality of chips are transferred to a predetermined portion of the pattern formation region of a semiconductor wafer in a first light exposure step. Subsequently, a second light-exposure step is performed, in which another circuit pattern of a single chip or a plurality of chips are transferred to an adjacent part by moving the light exposure apparatus. If the light exposure process mentioned above is repeated a plurality of times while moving the light-exposure position, the entire circuit pattern is transferred to the pattern formation region of the semiconductor wafer.
In this light exposure step, if the surface of the semiconductor wafer is not flat but significantly uneven, the distance between a lens of the pattern exposure apparatus and a light-receiving surface of the wafer varies from part to part. If the variance in distance exceeds a certain limitation, a so-called out-of-focus image is formed. As a result, a transfer pattern becomes blurred. The range of the distance within which no blurred image is formed, is called “the depth of focus” D. There is the following relationship between the depth of focus D, resolution R, an aperture ratio (N/A) of the lens of the stepper, and wavelength &lgr; of a light source:
R=K
1
×&lgr;/(
NA
) (1)
D=K
2
×&lgr;/(
NA
) (2)
where K
1
, K
2
are constants.
The resolution R in the aforementioned equation (1) corresponds to a minimum drawing width. The resolution R has been reduced as the semiconductor devices are integrated. To reduce the resolution R, the wavelength of the light source must be reduced. As a result, the depth of focus D is reduced. Since the depth of focus D is reduced, the surface of the wafer is required to be formed much flatter.
Therefore, a mechanism is devised to cope with the case where the degree of flatness of the wafer surface is low. The mechanism is a leveling function and used by setting it in the stepper. More specifically, leveling is made by setting a light-exposure reference plane on the wafer so as to minimize the variation in distance between the lens of the light exposure apparatus and sites of the light-receiving surface of the wafer (said variation is ascribed to the unevenness of the surface) in the region to be exposed to light at one time, and tilting the wafer such that the light-exposure reference plane matches with a light focus plane.
Recently, semiconductor devices have been integrated more and more. The integration of the semiconductor devices is attained by not only reducing the minimum drawing width but also increasing a chip size. This fact means that smaller images requiring low resolutions have to be drawn onto a larger area. To attain this, it is necessary to use a lens having a larger aperture and a smaller aberration. As a result, a higher cost is required not only to design the stepper lens system but also to fabricate the stepper employing such a lens system.
There is another system called “scan light exposure system”. In this system, the entire pattern drawn on the reticle is not transferred to the wafer at one time. Instead, a part of the pattern on the reticle is scanned from one end to the other end and transferred while the wafer is moved. The scan light exposure system has the following advantages. First, a large-size lens is not set in the stepper. Since the area to be exposed at one time (called “unit exposure area”) can be reduced, even if the wafer has an uneven surface, the uneven surface will not have a large effect upon transferring of the pattern. This means that the transferring pattern according to this system is the same as when the pattern is transferred to a substantially flat wafer surface.
When a wafer is manufactured, the surface of the wafer is usually polished with a polishing agent such as a colloidal silica to form a mirror surface. More specifically, the wafer surface is placed on a polishing cloth (urethane or non-woven cloth), and is swung and rotated while the wafer surface is pressurized. In this step, since weight is applied onto the wafer, the wafer is more or less sunk into the polishing cloth. The peripheral portion of a wafer edge is brought into contact with the polishing cloth at an angle. As a result, the edge of the peripheral portion of the wafer is selectively polished and rounded off. Therefore, the “rounded off portion” is inevitably formed in the peripheral portion of the wafer edge.
Since the “rounded off portion” is present, the flatness of the surface is significantly reduced on the peripheral portion. Therefore, it becomes very difficult to level the wafer surface of the peripheral portion in order to reduce the degree of the roughness of the surface, during the light exposure step. To explain in other words, leveling (tilting the wafer) is not performed regularly, with the result that a leveling error occurs more frequently.
There is another advantage of the scan light-exposure stepper. If a chip size is smaller than the area exposed to light from the stepper at one time, a plurality of chips can be simultaneously exposed to the light. Therefore, the time required for applying light to the entire surface of a wafer can be reduced. Since a light-exposure unit area is small, the light-exposure reference plane is more easily performed in accordance with the degree of roughness of the wafer surface.
Problems occur when a circuit pattern is transferred to the region including a peripheral portion of the wafer edge. We will now explain the problems with reference to
FIG. 1A
to FIG.
1
E.
FIG. 1A
is a plan view of a semiconductor wafer. The region surrounded by vertical lines
51
and horizontal lines
52
on the figure is an area which can be exposed to light at one time in a single scanning operation (called “unit scan region”). FIG.
1
B and
FIG. 1C
show enlarged plan views of the unit scan region.
FIG. 1D
is a cross-sectional view taken along the line
1
D—
1
D of FIG.
1
B.
FIG. 1E
is a cross sectional view taken along the line
1
E—
1
E of FIG.
1
C.
As shown in
FIG. 1A
, an edge exclusion line
54
is usually drawn inside an outer circumference
53
on the semiconductor wafer. The edge exclusion line
54
is used to divide between an effective element region (inside the line) and the “rounded off” peripheral edge portion (outside the line). Now, a case is assumed that a pattern drawn on a reticle is transferred onto the unit scan region (indicated by an open-circle ∘ in
FIG. 1A
) including the rounded off peripheral region by scanning a unit light exposure region
55
, as shown in
FIGS. 1B and 1C
.
When light is applied to an effective chip region alone (as shown in FIG.
1
B), the light-exposure reference plane is obtained relatively flat as shown in FIG.
1
D. Whereas, when light is applied to a region including an ineffective chip region (as shown in FIG.
1
C), the light-exposure reference plane is inclined as shown in FIG.
1
E. This is because the light-exposure reference plane is set so as to off set the “rounded off” surface of the
Kabushiki Kaisha Toshiba
Nguyen Henry Hung
LandOfFree
Pattern exposure apparatus for transferring circuit pattern... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pattern exposure apparatus for transferring circuit pattern..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern exposure apparatus for transferring circuit pattern... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3175482